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S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
by Daniel Nenni on 10-30-2023 at 10:00 am

Pic1

S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor. S7-19P not only accelerates the iterations of processor development but also simplifies other companies to realize … Read More


Developing Effective Mixed Signal Models. Innovation in Verification

Developing Effective Mixed Signal Models. Innovation in Verification
by Bernard Murphy on 10-30-2023 at 6:00 am

Innovation New

Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano… Read More


Keynote Speakers Announced for IDEAS 2023 Digital Forum

Keynote Speakers Announced for IDEAS 2023 Digital Forum
by Daniel Nenni on 10-26-2023 at 10:00 am

ideas 400X400

As we all know, hearing directly from the people who actually use EDA tools, people who are solving real world problems with the latest technologies are the best source of information. Thus EDA User group meetings are always first on my event list every year which brings us to Ansys Ideas.

Ansys User Group Meeting Features Technical

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Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
by Kalar Rajendiran on 10-25-2023 at 10:00 am

3D IC Cross Section Illustration

One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields… Read More


Generative AI for Silicon Design – Article 1 (Code My FSM)

Generative AI for Silicon Design – Article 1 (Code My FSM)
by Anshul Jain on 10-24-2023 at 10:00 am

Generative AI for Silicon Design

In today’s fast-paced world, innovation in semiconductor design is a constant demand. The need for quicker, more accurate, and innovative solutions has paved the way for exploring the potential of Generative AI (#GenerativeAI) in the realm of semiconductor design development. Can it be done? Hell yeah! In this article… Read More


SRAM design analysis and optimization

SRAM design analysis and optimization
by Daniel Payne on 10-24-2023 at 6:00 am

SRAM design cell min

Every year EDA vendor MunEDA hosts a user group meeting where engineers present how they used automation tools to improve their IC designs, and one presentation from Peter Huber of Infineon caught my attention, it was all about SRAM design optimization. Peter has authored papers at IEEE conferences and been issued patents related… Read More


Managing IP, Chiplets, and Design Data

Managing IP, Chiplets, and Design Data
by Daniel Payne on 10-23-2023 at 10:00 am

Managing IP min

Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked… Read More


Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines

Podcast EP189: A Look at the Q2 Electronic Design Market Data Report Results with Wally Rhines
by Daniel Nenni on 10-23-2023 at 8:00 am

Dan is joined by Dr. Walden Rhines. Wally is a lot of things, CEO of Cornami, board member, advisor to many and friend to all. For this discussion he is the Executive Sponsor of the SEMI Electronic Design Market Data report.

Dan explores the Q2 results summarized in the report with Wally. Overall growth was around 5%, a much lower number… Read More


100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers
by Kalar Rajendiran on 10-23-2023 at 6:00 am

112G Ethernet PHY IP EOE InterOp Demo JR5 0179

Electrical copper interconnects, once the backbone of data center networks, are facing growing challenges. Rapid expansion of AI and ML applications is driving a significant increase in cluster sizes within data centers, resulting in substantial demands for faster I/O capabilities. While the surge in I/O requirements is … Read More


Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam

Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
by Daniel Nenni on 10-20-2023 at 10:00 am

Dan is joined by Anand Thiruvengadam, director of product and business management and head of the Solutions and Go-to-Market functions for the memory market segment at Synopsys.

Anand discusses the substantial demands experienced by memory designers due to trends such as big data analytics. He describes how these demands impact… Read More