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Checklist to Ensure Silicon Interposers Don’t Kill Your Design

Checklist to Ensure Silicon Interposers Don’t Kill Your Design
by Dr. Lang Lin on 03-20-2023 at 10:00 am

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Traditional methods of chip design and packaging are running out of steam to fulfill growing demands for lower power, faster data rates, and higher integration density. Designers across many industries – like 5G, AI/ML, autonomous vehicles, and high-performance computing – are striving to adopt 3D semiconductor… Read More


CTO Interview: Dr. Zakir Hussain Syed of Infinisim

CTO Interview: Dr. Zakir Hussain Syed of Infinisim
by Daniel Nenni on 03-17-2023 at 6:00 am

Zakir Hussain Infinisim

Zakir Hussain is a co-founder of Infinisim and brings over 25 years of experience in the Electronic Design Automation industry. He was at Simplex Solutions, Inc. (acquired by Cadence) at its inception in 1995 through the end of 2000.  He has published numerous papers on verification and simulation and has presented at many industry… Read More


Must-attend webinar event: How better collaboration can improve your yield

Must-attend webinar event: How better collaboration can improve your yield
by Daniel Nenni on 03-16-2023 at 10:00 am

YieldHub Webinar

In today’s rapidly evolving semiconductor industry, the demand for high-quality and reliable semiconductors at a reasonable cost is increasing. This is why world-class yield management has become more and more important for fabless semiconductor companies and IDMs.

In a must-attend event, yieldHUB will be hosting… Read More


Accellera Update at DVCon 2023

Accellera Update at DVCon 2023
by Bernard Murphy on 03-16-2023 at 6:00 am

logo accellera min

I have a new-found respect for Lu Dai. He is a senior director of engineering at Qualcomm, with valuable insight into the ground realities of verification in a big semiconductor company. He is on the board of directors at RISC-V International and is chairman of the board of directors at Accellera, both giving him a top-down view of… Read More


Scaling the RISC-V Verification Stack

Scaling the RISC-V Verification Stack
by Bernard Murphy on 03-15-2023 at 6:00 am

RISC V verification stack

The RISC-V open ISA premise was clearly a good bet. It’s taking off everywhere, however verification is still a challenge. As an alternative to Arm, the architecture and functionality from multiple IP providers looks very competitive, but how do RISC-V providers and users ensure the same level of confidence we have in Arm? Arm … Read More


Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28

Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28
by Bob Smith on 03-10-2023 at 6:00 am

ESD Alliance Export Seminar 2023

Anyone interested in learning about general trade compliance concepts or how export control and sanction regulations affect the electronic systems design ecosystem will want to attend the upcoming ESD Alliance export seminar. It will be hosted by Ada Loo, chair of the ESD Alliance Export Committee and Cadence’s Group Director… Read More


Multi-Die Systems Key to Next Wave of Systems Innovations

Multi-Die Systems Key to Next Wave of Systems Innovations
by Kalar Rajendiran on 03-07-2023 at 10:00 am

Shift to Multi Die Systems is Happening Now

These days, the term chiplets is referenced everywhere you look, in anything you read and in whatever you hear. Rightly so because the chiplets or die integration wave is taking off. Generally speaking, the tipping point that kicked off the move happened around the 16nm process technology when large monolithic SoCs started facing… Read More


Calibre IC Manufacturing papers at SPIE 2023

Calibre IC Manufacturing papers at SPIE 2023
by Daniel Nenni on 03-07-2023 at 6:00 am

SPIE 2023 San Jose

The Siemens Calibre group was very busy last week at SPIE. Calling Calibre industry leading really is an understatement. Calibre is one of the reasons Moore’s Law has continued to this day. This tool is legendary. You can get more information on the Calibre landing page including product information, resource guide, blogs

Read More

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy

Defacto’s SoC Compiler 10.0 is Making the SoC Building Process So Easy
by Daniel Nenni on 03-02-2023 at 6:00 am

SoC Integration IP XACT RTL

We have been working with Defacto since 2016 and it has been quite a journey. Putting an entire system on a chip is a driving force in the semiconductor industry. With the complexity of designing a modern SoC constantly increasing, new tools and methodologies are required and it all starts with RTL.

Defacto Technologies is an innovativeRead More


HFSS Leads the Way with Exponential Innovation

HFSS Leads the Way with Exponential Innovation
by Matt Commens on 02-28-2023 at 10:00 am

HFSS Figure1

As engineers continue to design more complex systems with increasing frequency, the need for speed and capacity to solve these structures also increases. Over the years, HFSS has come a very long way and can now solve exponentially large structures with millions of unknowns. Ansys HFSS never stopped advancing,  continuing … Read More