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EDA

Electronic Design Automation

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An Approach to 20nm IC Design

An Approach to 20nm IC Design
by Daniel Payne on 07-17-2012 at 10:10 am
Categories: Cadence, EDA

Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.

Here’s… Read More

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How has 20nm Changed the Semiconductor Ecosystem?

How has 20nm Changed the Semiconductor Ecosystem?
by Daniel Nenni on 07-15-2012 at 7:30 pm
Categories: Cadence, EDA, Foundries, TSMC


What does mango beer have to do with semiconductor design and manufacturing? At a table of beer drinkers from around the world I would have never thought fruity beer would pass a taste test, not even close. As it turns out, the mango beer is very good! Same goes for 20nm planar devices. “Will not work”, “Will not yield”, “Will not scale”,… Read More

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Scoreboards and Results Predictors in UVM

Scoreboards and Results Predictors in UVM
by Daniel Nenni on 07-15-2012 at 10:56 am
Categories: EDA, Siemens EDA

If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case.

Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that… Read More

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Using Accurate Models to Debug Cellphones

Using Accurate Models to Debug Cellphones
by Paul McLellan on 07-13-2012 at 10:54 am
Categories: EDA

There is an interesting Gizmodo review of an HTC Android-based smartphone. The basically positive review (as good as the iPhone, best Android phone at the time) ends up with an update:UPDATE: After more extensive testing there’s something a little weird going on. You’ll probably only see this while gaming, but there’s… Read More

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Atrenta Technology Forum, Japan

Atrenta Technology Forum, Japan
by Paul McLellan on 07-11-2012 at 6:32 pm
Categories: EDA

The 1st Atrenta Technology Forum in Japan (well, it used to be the user group meeting, so it’s only the first in a very technical sense) is next week on July 19th from 1pm until 5.15pm. It will be held in the Shin-Yokohama Kokusai Hotel (how to access it here).

In the unlikely event that non-Japanese are reading this blog, here’s… Read More

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Using Synopsys Analysis Tools for AMS Design

Using Synopsys Analysis Tools for AMS Design
by Daniel Payne on 07-11-2012 at 12:05 pm
Categories: EDA, Synopsys

I attended the Synopsys webinar today for a tool called Custom Explorer Ultra (CXU). Product details on the Synopsys web site are here. The CXU tool would be used by AMS designers that want to setup, control and view results from simulators like HSPICE, CustomSim or VCS on transistor-level and AMS designs.… Read More

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Enabling 3D-IC Integration

Enabling 3D-IC Integration
by Daniel Nenni on 07-10-2012 at 9:00 pm
Categories: EDA, Synopsys

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As 2D device scaling becomes impractical, 3D-IC integration is emerging as the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality. Some of the benefits of 3D-IC, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints,… Read More

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SNUG in Asia, US East Coast

SNUG in Asia, US East Coast
by Paul McLellan on 07-10-2012 at 8:05 pm
Categories: EDA, Synopsys

If you are in Asia then the Synopsys user group SNUG is coming up, soon in Japan and next month in China. Actually if you are in India I’m afraid you already missed it last month, just after DAC.

SNUG Japan is on 12th July in a couple of days time from 10am until 8pm in Tokyo.

In China there are 3 between August 14th and 21st

  • Beijing 北京
… Read More
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Formal Going Mainstream

Formal Going Mainstream
by Paul McLellan on 07-10-2012 at 7:29 pm
Categories: EDA
3 Comments

In Mike Muller’s keynote at DAC he wanted to make formal approaches an integral part of writing RTL. After all, formal captures design intent and then, at least much of the time, can verify whether the RTL written actually matches that intent. Today, formal is not used that way and is typically something served “on the side” by specialist… Read More

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SPICE Timing Correlation for IC Place and Route

SPICE Timing Correlation for IC Place and Route
by Daniel Payne on 07-10-2012 at 10:35 am
Categories: EDA

SPICE circuit simulation is used for transistor-level analysis while Place and Route tools are typically used to connect cells and blocks of an SoC, so why would there be a connection between these two EDA tools?

I read a press release today from ATopTech and Berkeley Design Automation that talked about how SPICE and P&R are … Read More