Multi Die Webinar 800x100 High Quality
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EDA

Electronic Design Automation

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Hardware Configuration Management approach awarded a Patent

Hardware Configuration Management approach awarded a Patent
by Daniel Payne on 09-13-2011 at 11:21 am
Categories: Cliosoft, EDA

Hardware designers use complex EDA tool flows that have collections of underlying binary and text files. Keeping track of the versions of your IC design can be a real issue when your projects use teams of engineers. ClioSoft has been offering HCM (Hardware Configuration Management) tools that work in the most popular flows of: … Read More

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Another Up Year in a Down Economy for Tanner EDA

Another Up Year in a Down Economy for Tanner EDA
by Daniel Payne on 09-13-2011 at 11:00 am
Categories: EDA, Tanner EDA

Almost every week I read about a slowing world economy, yet in EDA we have some bright spots to talk about, like Tanner EDA finishing its 24th year with an 8% increase in revenue. More details are in the press release from today.

I spoke with Greg Lebsack, President of Tanner EDA on Monday to ask about how they are growing. Greg has been… Read More

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When analog/RF/mixed-signal IC design meets nanometer CMOS geometries!

When analog/RF/mixed-signal IC design meets nanometer CMOS geometries!
by Daniel Nenni on 09-13-2011 at 9:22 am
Categories: EDA

In working with TSMC and GlobalFoundries on AMS design reference flows I have experienced first hand the increasing verification challenges of nanometer analog, RF, and mixed-signal circuits. Tools in this area have to be both silicon accurate and blindingly fast! Berkeley Design Automation is one of the key vendors in this … Read More

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Synopsys STAR Webinar, embedded memory test and repair solutions

Synopsys STAR Webinar, embedded memory test and repair solutions
by Eric Esteve on 09-12-2011 at 8:16 am
Categories: IP, Synopsys

The acquisitions of Virage Logic by Synopsys in 2010, have allowed building a stronger, diversified IP port-folio, including the embedded SRAM, embedded non-volatile memory and embedded test and repair solution. Looking back in time, I remember the end of the 80’s: at that time the up-to-date solution to embed SRAM in your ASIC… Read More

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Cadence ClosedAccess

Cadence ClosedAccess
by Paul McLellan on 09-11-2011 at 4:00 pm
Categories: Cadence, EDA

There are various rumors around about Cadence starting to close up stuff that has been open for a long time. Way back in the midst of time, as part of the acquisition of CCT, the Federal Trade Commission forced Cadence to open up LEF/DEF and allow interoperability of Cadence tools (actually only place and route) I believe for 10 years.… Read More

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2.5D and 3D designs

2.5D and 3D designs
by Paul McLellan on 09-07-2011 at 1:54 pm
Categories: Ansys, Inc., EDA

Going up! Power and performance issues, along with manufacturing yield issues, limit how much bigger chips can get in two dimensions. That, and the fact that you can’t manufacture two different processes on the same wafer, mean that we are going up into the third dimension.

The simplest way is what is called package-in-package… Read More

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Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics

Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics
by Daniel Payne on 09-05-2011 at 3:37 pm
Categories: EDA, Foundries, GlobalFoundries, Siemens EDA

Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More

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What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?

What changes to expect in Verification IP landscape after Synopsys acquisition of nSys?
by Eric Esteve on 09-05-2011 at 4:53 am
Categories: IP, Synopsys

Even if nSys acquisition by Synopsys will not have a major impact on Synopsys’ balance sheet, it is a kind of earthquake in the Verification market landscape. After the Denali acquisition by Cadence in 2010, nSys was most probably the market leader in verification IP, if we look at the independent VIP providers (excluding Cadence).… Read More

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I love you, you love me, we’re a happy family…

I love you, you love me, we’re a happy family…
by Paul McLellan on 08-31-2011 at 8:00 pm
Categories: Arm, Cadence, EDA, Foundries, GlobalFoundries, Siemens EDA, Synopsys

The CEO panel at the 2nd GTC wasn’t especially enlightening. The theme was that going forward will require cooperation for success and everyone was really ready to cooperate.

The most interesting concept was Aart talking about moving from what he called “scale complexity” aka Moore’s law to what he … Read More

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Nanometer Circuit Verification Forum

Nanometer Circuit Verification Forum
by Daniel Nenni on 08-29-2011 at 2:33 pm
Categories: EDA

Verifying circuits on advanced process nodes has always been difficult, and it’s no easier with today’s nanometer CMOS processes. There’s a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom … Read More