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EDA Tool Flow at MoSys Plus Design Data Management

EDA Tool Flow at MoSys Plus Design Data Management
by Daniel Payne on 01-20-2012 at 4:50 pm

I’ve read about MoSys over the years and had the chance this week to interview Nani Subraminian, Engineering Manager about the types of EDA tools that they use and how design data management has been deployed to keep the design process organized. My background includes both DRAM and SRAM design, so I’ve been curious… Read More


What is a Hierarchical SPICE Circuit Simulator?

What is a Hierarchical SPICE Circuit Simulator?
by Daniel Payne on 01-19-2012 at 2:56 pm

Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:

  • Mask Data
  • IC Layout
  • Schematic Netlists
  • Gate level netlists
  • RTL netlists

But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More


Low-power IC design in Switzerland

Low-power IC design in Switzerland
by Daniel Payne on 01-18-2012 at 7:17 pm

My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More


Addressing the Challenges of Tomorrow’s SoC Design

Addressing the Challenges of Tomorrow’s SoC Design
by Paul McLellan on 01-17-2012 at 5:28 pm

For the next few days Atrenta is running a series of 30 minute live webinars to discuss the new solutions and approaches that are required to improve the way SoC designs are created and modified.

The webinars are at the following times:

  • Jan 17th, 7-7.30am PST (sorry you missed that one)
  • January 18th 7.30-8pm PST (and January 19th in
Read More

Chip-Package-System workshops

Chip-Package-System workshops
by Paul McLellan on 01-17-2012 at 4:30 pm

Chips, packages and circuit boards (systems, hence CPS) used to be three separate domains with their own tools that barely interacted at all. If you were lucky, reassigning a pin on a package wouldn’t have to be done manually in all 3 places. But now, from a signal integrity, noise, power point of view these three domains must… Read More


#49 Design Automation Conference Deadlines

#49 Design Automation Conference Deadlines
by Paul McLellan on 01-14-2012 at 10:53 pm

Note that there are several DAC deadlines coming up in the next couple of weeks.

The deadline for user track submissions is January 17th (next Tuesday). Submission requires an extended abstract. See here for details.

The deadline for DAC workshops is January 19th (next Thursday). A proposal is required. See here for details.

The… Read More


Needham growth conference

Needham growth conference
by Paul McLellan on 01-13-2012 at 6:00 am

One of the fun things when a company gets big but is still private, like Atrenta, is that you start to get invited to events like the Needham Growth Conference that took place earlier this week in New York. When I ran Compass Design Automation, which at the time was about $55M in revenue, I remember going to a couple of these events. At … Read More


EDAC reports Q3

EDAC reports Q3
by Paul McLellan on 01-12-2012 at 7:49 pm

EDAC (EDA consortium) market statistics service announced the data for Q3 of 2011. Revenue increased 18.1% (versus 2010) to $1543.9 million. Sequentially (versus Q2) revenue increase 7.4%. Annualized, that puts EDA at over $6B for, I belive, the first time ever. Wally Rhines, who is EDAC chair (and CEO of Mentor) commented that… Read More


Advanced Memory Cell Characterization with Calibre xACT 3D

Advanced Memory Cell Characterization with Calibre xACT 3D
by SStalnaker on 01-12-2012 at 7:18 pm

Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.

To meet these new requirements for performance and power, memory… Read More


Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
by Eric Esteve on 01-12-2012 at 9:45 am

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More