SILVACO 051525 Webinar 800x100 v2
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4117
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4117
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Webinar: how to reduce mobile device cost and board space with LLI

Webinar: how to reduce mobile device cost and board space with LLI
by Eric Esteve on 06-24-2012 at 2:46 am
Categories: Arteris, EDA, IP, Synopsys

LLI Specification has been officially released by the MIPI Alliance, at the occasion of the Mobile World Congress in Barcelona, this year. As indicated by the name, the round-trip latency of the LLI inter-chip connection is fast enough for a mobile phone modem to share an application processor’s memory while maintaining… Read More

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Designing a Wafer-Scale Image Sensor for use in X-Rays

Designing a Wafer-Scale Image Sensor for use in X-Rays
by Daniel Payne on 06-22-2012 at 1:32 pm
Categories: EDA, Tanner EDA

At Intel we mused about designing wafer-scale integration (WSI) back in the 70’s however I just learned about how Dr.Renato Turchetta at the Science and Technology Facilities Council (STFC) designed a wafer-scale imaging sensor chip for X-Ray applications. I was also able to interview Dr. Turchetta to learn more about… Read More

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EDA Tools to Optimize Memory Design

EDA Tools to Optimize Memory Design
by Daniel Payne on 06-21-2012 at 8:15 pm
Categories: EDA, Solido

I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they’ve expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more… Read More

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Double Patterning Technology at DAC

Double Patterning Technology at DAC
by Daniel Payne on 06-20-2012 at 5:12 pm
Categories: EDA, Siemens EDA
6 Comments

David Abercrombie from Mentor Graphics met with me on Tuesday at DAC to provide an update on DPT – Double Patterning Technology, something new required for several layers starting at the 20nm node in order to get any IC yield. DPT is also part of Multiple-Patterning.… Read More

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IPL Alliance at DAC

IPL Alliance at DAC
by Daniel Payne on 06-20-2012 at 3:25 pm
Categories: EDA, Synopsys

Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me,… Read More

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Atrenta Aquires NextOp

Atrenta Aquires NextOp
by Paul McLellan on 06-20-2012 at 10:00 am
Categories: EDA

Atrenta announced today that it is acquiring NextOp Software. NextOp sells a tool BugScope that provides assertion synthesis technology. This complements Atrenta’s SpyGlass products for improving the process for design of complex semiconductor IP and SoCs.

I went to Atrenta’s office to talk to Ajoy Bose (CEO)… Read More

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Shape-based IC Routing at DAC

Shape-based IC Routing at DAC
by Daniel Payne on 06-19-2012 at 8:05 pm
Categories: EDA
2 Comments

IC place and route is a big challenge so we see many EDA companies creating tools. On Tuesday at DAC I met with Dave Noble of Pulsic to get an update.

Notes

Dave Noble, VP Operations (EDA since 2003), Sperry Univac since 1974
– had been an EDA distributor for Pulsic as well

More leads qualified on Monday than all days of last year … Read More

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3D Thermal and Mechanical Stress for IC Packaging

3D Thermal and Mechanical Stress for IC Packaging
by Daniel Payne on 06-19-2012 at 8:02 pm
Categories: EDA, Events

3D has been a growing buzz word in IC design and packaging for several years now, so it’s refreshing to actually find an EDA vendor that has developed tools to help analyze something like 3D thermal and mechanical stress at DAC. … Read More