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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4174
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4174
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

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Power, Signal, Thermal and EMI signoff

Power, Signal, Thermal and EMI signoff
by Paul McLellan on 08-28-2012 at 1:55 pm
Categories: Ansys, Inc., EDA
3 Comments

Increasingly the challenge with SoCs, especially for mobile, is not getting the performance high enough but doing so in a power-efficient manner. Handheld devices running multiple apps need high-speed processors that consume extremely low levels of power both in operating and standby modes. In the server farm, the limit is … Read More

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SpringSoft Laker vs Tanner EDA L-Edit

SpringSoft Laker vs Tanner EDA L-Edit
by Daniel Nenni on 08-26-2012 at 7:00 pm
Categories: EDA, Tanner EDA
3 Comments

Daniel Payne recently blogged some of the integration challenges facing Synopsys with their impending acquisition of SpringSoft. On my way back from San Diego last week I stopped by Tanner EDA to discuss an alternative tool flow for users who find themselves concerned about the Laker Custom Layout road map.

Design of the analog… Read More

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IP Wanna Go Fast, Core Wanna Not Rollover

IP Wanna Go Fast, Core Wanna Not Rollover
by Don Dingee on 08-23-2012 at 8:15 pm
Categories: EDA, IP, Synopsys
2 Comments

At a dinner table a couple years ago, someone quietly shared their biggest worry in EDA. Not 2GHz, or quad core. Not 20nm, or 450mm. Not power, or timing closure. Call it The Rollover. It’s turned out to be the right worry.

Best brains spent inordinate hours designing and verifying a big, hairy, heavy breathing processor core to do … Read More

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A Brief History of ASIC, part II

A Brief History of ASIC, part II
by Paul McLellan on 08-23-2012 at 8:00 pm
Categories: EDA

All semiconductor companies were caught up in ASIC in some way or another because of the basic economics. Semiconductor technology allowed medium sized designs to be done, and medium sized designs were pretty much all different. The technology didn’t yet allow whole systems to be put on a single chip. So semiconductor companies… Read More

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Book Review: Mixed-Signal Methodology guide

Book Review: Mixed-Signal Methodology guide
by Daniel Payne on 08-23-2012 at 4:00 pm
Categories: Cliosoft, EDA
4 Comments

Almost every SoC has multiple analog blocks so AMS methodology is an important topic to our growing electronics industry. Authored by Jess Chen (Qualcomm), Michael Henrie (Cliosoft), Monte Mar (Boeing) and Mladen Nizic (Cadence), the book is subtitled: Advanced Methodology for AMS IP and SoC Design, Verification and Implementation… Read More

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Book Review: Mixed-Signal Methodology Guide

Book Review: Mixed-Signal Methodology Guide
by Daniel Payne on 08-23-2012 at 4:00 pm
Categories: Cadence, EDA
10 Comments

Almost every SoC has multiple analog blocks so AMS methodology is an important topic to our growing electronics industry. Authored by Jess Chen (Qualcomm), Michael Henrie (Cliosoft), Monte Mar (Boeing) and Mladen Nizic (Cadence), the book is subtitled: Advanced Methodology for AMS IP and SoC Design, Verification and Implementation… Read More

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Debugging Subtle Cache Problems

Debugging Subtle Cache Problems
by Paul McLellan on 08-22-2012 at 5:11 pm
Categories: Arm, EDA, IP

When I worked for virtual platform companies, one of the things that I used to tell prospective customers was that virtual prototypes were not some second-rate approach to software and hardware development to be dropped the moment real silicon was available, that in many ways they were better than the real hardware since they had… Read More

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Synopsys up to $1.75B

Synopsys up to $1.75B
by Paul McLellan on 08-22-2012 at 4:24 pm
Categories: EDA, Synopsys
5 Comments

Synopsys announced their results today. With Magma rolled in (but not yet SpringSoft since that hasn’t technically closed) they had revenue of $443M up 15% from $387M last year. This means that they are all but a $1.75B company and a large part of the entire EDA industry (which I think of as being $5B or so, depending on just what… Read More

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Cadence at 20nm

Cadence at 20nm
by Paul McLellan on 08-21-2012 at 8:10 pm
Categories: Cadence, EDA

Cadence has a new white paper out about the changes in IC design that are coming at 20nm. One thing is very clear: 20nm is not simply “more of the same”. All design, from basic standard cells up to huge SoCs has several new challenges to go along with all the old ones that we had at 45nm and 28nm.

I should emphasize that the paper… Read More

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A Brief History of ASIC, part I

A Brief History of ASIC, part I
by Paul McLellan on 08-21-2012 at 7:00 pm
Categories: EDA

In the early 1980s the ideas and infrastructure for what would eventually be called ASIC started to come together. Semiconductor technology had reached the point that a useful number of transistors could be put onto a chip. But unlike earlier, when a chip only held a few transistors and thus could be used to create basic generic building… Read More