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EDA

Electronic Design Automation

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Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification

Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification
by Daniel Nenni on 11-12-2012 at 7:00 pm
Categories: EDA


Verification and AMS are top search terms on SemiWiki so clearly designers have a pressing need for fast and accurate verification of today’s mixed-signal SoCs that include massive digital blocks and precision analog/RF circuits. They need simulation performance to verify the mixed-signal functionality, and they need nanometer… Read More

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Cadence sets the Global Standards in VIP for AMBA based SoC

Cadence sets the Global Standards in VIP for AMBA based SoC
by Eric Esteve on 11-12-2012 at 11:48 am
Categories: Cadence, IP

We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More

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Next Generation FPGA Prototyping

Next Generation FPGA Prototyping
by Paul McLellan on 11-12-2012 at 7:00 am
Categories: EDA, FPGA, Synopsys

One technology that has quietly gone mainstream in semiconductor design is FPGA prototyping. That is, using an FPGA version of the design to run extensive verification. There are two approaches to doing this. The first way is simply to build an prototype board, buy some FPGAs from Xilinx or Altera and do everything yourself. The… Read More

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Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm
Categories: EDA, Synopsys

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
[LIST=1]

  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
    • … Read More
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    Carbon has Six Weeks of ARM, not to Mention Imagination and MIPS

    Carbon has Six Weeks of ARM, not to Mention Imagination and MIPS
    by Paul McLellan on 11-09-2012 at 12:18 pm
    Categories: Arm, EDA, IP

    As George E.P. Box said, “essentially all models are wrong but some are useful.” That is certainly the case with Carbon’s models. For processors they have two models, one that is fast (but not timing-accurate) and one that is accurate (but not fast). But both are useful.

    Carbon attended the ARM TechCon in Santa… Read More

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    ICCAD at 30: Alberto Looks Back and Forward

    ICCAD at 30: Alberto Looks Back and Forward
    by Paul McLellan on 11-08-2012 at 8:10 pm
    Categories: EDA, Events

    At ICCAD earlier this week, CEDA sponsored a talk by Alberto Sangiovanni-Vincentelli looking back over the last 30 years (it is the 30th anniversary of ICCAD) and looking to the future. As is always the case in these sorts of presentations, the retrospective contained a lot more detail than the going forward part. Clayton Christensen… Read More

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    IJTAG, Testing Large SoCs

    IJTAG, Testing Large SoCs
    by Paul McLellan on 11-08-2012 at 5:57 pm
    Categories: EDA, Siemens EDA

    Test is the Rodney Dangerfield of EDA, it doesn’t get any respect. All designs need to be tested but somehow synthesis, routing, analog layout and the rest are the sexy areas. In my spoof all purpose EDA keynote address I even dissed it:You are short on time so slip in a quick mention of manufacturing test. Who knows anything … Read More

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    ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program

    ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program
    by Eric Esteve on 11-07-2012 at 12:17 pm
    Categories: EDA, Foundries, TSMC

    More than one year old now, TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. This soft IP quality program has been the first to be initiated by a Silicon foundry on other than “Hard IP”,… Read More

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    Solido and TSMC for 6-Sigma Memory Design

    Solido and TSMC for 6-Sigma Memory Design
    by Daniel Nenni on 11-06-2012 at 8:30 pm
    Categories: EDA, Solido

    Solido Design Automation and TSMC recently published an article in EE Times describing how Solido’s High-Sigma Monte Carlo tool is used with TSMC PDK’s to achieve high-yield, high-performance memory design. This project has been a big part of my life for the past three years and it is time for a victory lap!

    In TSMC 28nm, 20nm and … Read More

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    Embedding 100K probes in FPGA-based prototypes

    Embedding 100K probes in FPGA-based prototypes
    by Don Dingee on 11-06-2012 at 8:15 pm
    Categories: EDA

    As RTL designs in FPGA-based ASIC prototypes get bigger and bigger, the visibility into what is happening inside the IP is dropping at a frightening rate. Where designers once had several hundred observation probes per million gates, those same several hundred probes – or fewer if deeper signal captures are needed – are now spread… Read More