Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Fixing Double-patterning Errors at 20nm

Fixing Double-patterning Errors at 20nm
by Paul McLellan on 01-16-2013 at 10:54 pm
Categories: EDA, Siemens EDA

David Avercrombie of Mentor won the award for the best tutorial at the 2012 TSMC OIP for his presentation, along with Peter Hsu of TSMC, on Finding and Fixing Double Patterning Errors in 20nm. The whole presentation along with the slides is now available online here. The first part of the presentation is an introduction to double … Read More

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Mentor @ the TSMC Open Innovation Platform Forum

Mentor @ the TSMC Open Innovation Platform Forum
by glforte on 01-16-2013 at 6:16 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

At TSMC’s Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.

Finding and Fixing Double Patterning Errors in… Read More

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A Brief History of Apache Design

A Brief History of Apache Design
by Daniel Nenni on 01-16-2013 at 3:00 pm
Categories: Ansys, Inc., EDA

Apache Design Solutions was founded in 2001 by Andrew Yang and three researchers from HP Labs (Norman Chang, Shen Lin, Weize Xie). They realized that engineers striving to meet the goal of increased device miniaturization, as defined by Moore’s Law, would eventually hit stumbling blocks in their progress. The founding team believed… Read More

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Is the RTL Design Flow Broken?

Is the RTL Design Flow Broken?
by Daniel Payne on 01-15-2013 at 11:02 am
Categories: EDA

I’ve taught Verilog classes and used logic synthesis tools for ASIC and FPGA designs, so was interested to hear about Oasys Design Systems. I attended their webinar at 9AM today, so I’ll share what I learned about their approach to logical and physical synthesis. This approach competes with tools like Design Compiler… Read More

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IP vendors enable SuperSpeed USB IP take off in 2012

IP vendors enable SuperSpeed USB IP take off in 2012
by Eric Esteve on 01-15-2013 at 5:09 am
Categories: IP, Synopsys

SuperSpeed USB has been clearly ranked in the Interface protocols winner list, see this previous post. It could be interesting to dig into this IP market segment, determine in which applications USB 3.0 has been successfully deployed and who are the IP vendors serving this market, enabling SuperSpeed USB to take off.

SuperSpeed… Read More

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ESD Check Methodology

ESD Check Methodology
by Paul McLellan on 01-11-2013 at 5:12 pm
Categories: Ansys, Inc., EDA

In Pune at the start of the month, Norman Chang, Ting-Sheng Ku, Jai Pollayil of Apache/Ansys and NVIDIA presented and ESD check methodologywith Fast Full-chip Static and Macro-level Dynamic Solutions . ESD stands for Elecro-Static Discharge and is basically injecting very high static voltages (think how your hand gets charged… Read More

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Predictions are hard, especially about the future

Predictions are hard, especially about the future
by Paul McLellan on 01-11-2013 at 11:26 am
Categories: EDA

I was asked to make some predictions about the EDA, semiconductor and electronic systems markets for 2013. I decided that it would be more fun to make some plausible predictions, some of which will be right, rather than go for anodyne predictions (“Cadence will acquire a couple of startups”) which are uninformative,… Read More

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A Brief History of Synopsys DesignWare ® IP

A Brief History of Synopsys DesignWare ® IP
by Daniel Nenni on 01-11-2013 at 9:00 am
Categories: IP, Synopsys

Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More

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Reducing Dynamic and Static Power in Memories

Reducing Dynamic and Static Power in Memories
by Paul McLellan on 01-10-2013 at 3:46 pm
Categories: EDA

Sequential approaches to power reduction work well on logic implemented using standard cells. But part of every SoC, sometimes a very large part, is taken up with embedded memories for which alternative approaches are required. Not only do these memories occupy up to half of the area they also account for as much as 75% of the power… Read More

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Global Design Closure

Global Design Closure
by Paul McLellan on 01-09-2013 at 8:34 pm
Categories: EDA

Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.


SoCs are really put together in two … Read More