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EDA

Electronic Design Automation

Posted on

Software Driven Power Analysis

Software Driven Power Analysis
by Paul McLellan on 02-03-2013 at 8:15 pm
Categories: Arm, EDA, IP

Power is a fundamentally hard problem. When you have finished the design, you have accurate power numbers but can’t do anything about them. At the RTL level you have some power information but it is often too late to make major architectural changes (add an offload audio-processor, for example). Early in the design, making… Read More

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Help, my IP has fallen and can’t get up

Help, my IP has fallen and can’t get up
by Don Dingee on 02-03-2013 at 8:10 pm
Categories: EDA, FPGA, IP, Synopsys

We’ve been talking about the different technologies for FPGA-based SoC prototyping a lot here in SemiWiki. On the surface, the recent stories all start off pretty much the same: big box, Xilinx Virtex-7, wanna go fast and see more of what’s going on in the design. This is not another one of those stories. I recently sat down with Mick… Read More

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A Brief History of ClioSoft

A Brief History of ClioSoft
by Daniel Payne on 02-03-2013 at 8:05 pm
Categories: Cliosoft, EDA

In the 1990s, software developers were established users of software configuration management (SCM) tools such as open source RCS/CVS or of commercial systems such as Clearcase. Hardware designers, however, managed design data in ad hoc home-grown ways. ClioSoft’s founder, Srinath Anantharaman, recognized that hardware… Read More

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Seeing inside SoC designs, from the beginning

Seeing inside SoC designs, from the beginning
by Don Dingee on 01-31-2013 at 8:10 pm
Categories: EDA

Engineers have this fascination with how things work. They are thrilled to tear stuff apart, and sometimes to even be able to put it back together afterwords. So I can keep my recovering engineer card, I thought I’d take a few moments and look inside a technology Daniel Payne and I have been covering here, exploring where the idea started… Read More

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TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm
Categories: EDA

Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling … Read More

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Dynamic/Leakage Power Reduction in Memories

Dynamic/Leakage Power Reduction in Memories
by Daniel Nenni on 01-31-2013 at 8:05 pm
Categories: EDA

Embedded memories have an important impact on power. SoCs that integrate multiple functions on a single silicon die are at the heart of many electronic devices. As process geometries have scaled, design teams have used more and more of the additional silicon real estate available to integrate embedded memories that serve as scratch-pads,… Read More

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Building Energy-Efficient ICs from the Ground Up

Building Energy-Efficient ICs from the Ground Up
by Daniel Payne on 01-31-2013 at 6:02 pm
Categories: Cadence, EDA

My oldest son just upgraded Smart Phones from a 3″ display to a 4.5″ display and was shocked to discover that his battery barely lasted 8 hours, so I welcomed him to the reality of limited battery life in modern SoC-based mobile devices. There is some hope in increasing battery life for our consumer-oriented devices … Read More

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Going to DAC 2013 in Austin? The Country’s Best Barbecue is a 20 Minute Walk

Going to DAC 2013 in Austin? The Country’s Best Barbecue is a 20 Minute Walk
by Paul McLellan on 01-30-2013 at 8:05 pm
Categories: EDA, Events

Going to DAC? I just booked my plane ticket last weekend since flights from the Bay Area to wherever DAC is are so often overbooked. It’s in Austin this year in case you’ve been living under a rock. There are lots of reasons to go, from the academic conference to the world’s biggest EDA exhibition. And here is one … Read More

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Catch Jasper at SemiIsrael Verification Day and at DVCon 2013

Catch Jasper at SemiIsrael Verification Day and at DVCon 2013
by Paul McLellan on 01-30-2013 at 4:08 pm
Categories: EDA

Jasper is presenting at both ends of the world at both ends of February.

First in Israel, it is SemiIsrael Verification Day 2013 on February 5th (next Tuesday) at Green House in Tel Aviv.

  • Zihad Hanna, VP of Research and Chief Architect and General Manager of Jasper Israel will be talking about Security Formal Verification of Hardware
… Read More
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Virtuoso is 20nm-ready

Virtuoso is 20nm-ready
by Paul McLellan on 01-30-2013 at 1:47 pm
Categories: Cadence, EDA

I already talked about how Cadence is splitting Virtuoso into two. Anyway, it is now officially announced. The 6.1 version will continue to be developed as a sort of Virtuoso classic for people doing designs off the bleeding edge that don’t require the new features. And a new Virtuoso 12.1 intended for people doing 20nm and… Read More