CAST Compression IP Webinar 800x100 (2)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4178
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4178
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)
EDA

Electronic Design Automation

Posted on

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion
by Eric Esteve on 03-07-2013 at 7:47 am
Categories: IP, Synopsys

We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More

Posted on

Lithography from Contact Printing to EUV, DSA and Beyond

Lithography from Contact Printing to EUV, DSA and Beyond
by Paul McLellan on 03-05-2013 at 6:21 pm
Categories: EDA, Events

I used my secret powers (being a blogger will get you a press pass) to go to the first day of the SPIE conference on advanced lithography a couple of weeks ago. Everything that happens to with process nodes seems to be driven by lithography, and everything that happens in EDA is driven by semiconductor process. It is the place to find … Read More

Posted on

Verification the Mentor Way

Verification the Mentor Way
by Paul McLellan on 03-05-2013 at 3:05 pm
Categories: EDA, Siemens EDA

During DVCon I met with Steve Bailey to get an update on Mentor’s verification. They were also announcing some new capabilities. I also attended Wally Rhines keynote (primarily about verification of course, since this was DVCon; I blogged about that here) and the Mentor lunch (it was pretty much Mentor all day for me) on the… Read More

Posted on

Watch the Clock

Watch the Clock
by Paul McLellan on 03-05-2013 at 2:24 pm
Categories: Ansys, Inc., EDA

Clock gating is one of the most basic weapons in the armoury for reducing dynamic power on a design. All modern synthesis tools can insert clock gating cells to shut down clocking to registers when the contents of the register are not changing. The archetypal case is a register which sometimes loads a new value (when an enable signal… Read More

Posted on

Integrating Formal Verification into Synthesis

Integrating Formal Verification into Synthesis
by Paul McLellan on 03-05-2013 at 1:29 pm
Categories: EDA

Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. But designs are getting very large and formal verification is a complex tool to use, especially if the design is too large for the formal tool… Read More

Posted on

Image Sensor Design for IR at Senseeker

Image Sensor Design for IR at Senseeker
by Daniel Payne on 03-05-2013 at 10:30 am
Categories: EDA, Tanner EDA

Image sensors are all around us with the cell phone being a popular example, and 35mm DSLR camera being another one. Last week I spoke with Kenton Veeder, an engineer at Senseeker that started his own image sensor IP and consulting services company. Instead of focusing on the consumer market, Kenton’s company does sensor … Read More

Posted on

Cavium Adopts JasperGold Architectural Modeling

Cavium Adopts JasperGold Architectural Modeling
by Paul McLellan on 03-05-2013 at 7:00 am
Categories: EDA

Cavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.

Cavium have… Read More

Posted on

Synopsys ♥ FinFETs

Synopsys ♥ FinFETs
by Daniel Nenni on 03-03-2013 at 6:00 pm
Categories: EDA, Synopsys

FinFETs are fun! They certainly have kept me busy writing over the past year about the possibilities and probabilities of a disruptive technology that will dramatically change the semiconductor ecosystem. Now that 14nm silicon is making the rounds I will be able to start writing about the realities of FinFETs which is very exciting!… Read More

Posted on

DVCon 2013 – Hope For EDA Trade Shows

DVCon 2013 – Hope For EDA Trade Shows
by Randy Smith on 03-03-2013 at 2:04 pm
Categories: EDA, Events

Those of us who spend a lot of time at EDA marketing events cannot help but notice the dramatic shrinking of the floor space, and to some extent attendance, at the major EDA shows such as DAC and DATE. DAC used to occupy both the north and south halls of Moscone Center when in San Francisco, but now only takes up one hall. So, I did not have… Read More

Posted on

TSMC ♥ Atrenta (Soft IP Webinar)

TSMC ♥ Atrenta (Soft IP Webinar)
by Daniel Nenni on 03-02-2013 at 4:00 pm
Categories: EDA, Sonics, TSMC

Back in 2011, TSMC announced it was extending its IP Alliance Program to include soft, or synthesizable IP. Around that time it was also announced that Atrenta’s SpyGlass platform would be used as the sole analysis tool to verify the completeness and quality of soft IP before being admitted to the program. Since then, the … Read More