Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Applied Power Electronics Conference & Exposition 2014: "Less Power"

Applied Power Electronics Conference & Exposition 2014: "Less Power"
by Bill Jewell on 03-27-2014 at 11:00 pm
Categories: EDA, Semiconductor Intelligence

On the television show “Home Improvement”, Tim Allen’s character always sought “more power” for whatever project he was working on. The theme of the Applied Power Electronics Conference and Exposition (APEC) 2014 could have been “less power”. APEC 2014 featured five days of seminars and sessions including professional education,… Read More

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IP Challenges, FinFET, 3D-IC, and FD-SOI Updates

IP Challenges, FinFET, 3D-IC, and FD-SOI Updates
by Daniel Nenni on 03-27-2014 at 10:00 am
Categories: EDA, Events, IP

Semiwiki is proud to be a sponsor of EDPS 2014:

April 17 & 18, 2014
Monterey Beach Hotel, Monterey, CA

Sponsored by:
IEEE Computer Society of Silicon Valley (CS-SCV)
IEEE Computer Society
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)

The Electronic Design Processes Symposium… Read More

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Early RTL Power Analysis and Reduction

Early RTL Power Analysis and Reduction
by Daniel Payne on 03-26-2014 at 4:48 pm
Categories: Ansys, Inc., EDA

Power analysis and reduction for SoC designs is a popular topic because of our consumer electronics dominated economy, and the need to operate devices on a battery source for the maximum time before a recharge. Just from my desk I can see multiple battery-powered devices: Laptop, tablet, smart phone, e-book reader, bluetooth … Read More

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Book review: “shift left” with virtual prototypes

Book review: “shift left” with virtual prototypes
by Don Dingee on 03-26-2014 at 1:00 pm
Categories: IP, Synopsys

Shipping a product with complete software support at official release is a lot more difficult than it sounds. Inevitably, there is less than enough hardware to go around, and what little there is has to fill the needs of hardware designers, test and certification engineers, software development teams, systems integration teams,… Read More

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SNUG and IC Compiler II

SNUG and IC Compiler II
by Paul McLellan on 03-25-2014 at 4:04 pm
Categories: EDA, Synopsys

I have been at SNUG for the last couple of days. The big announcement is IC Compiler II. It was a big part of Aart’s keynote and Monday lunch featured all the lead customers talking about their experience with the tool.

The big motivation for IC Compiler II was to create a fully multi-threaded physical design tool that will scale… Read More

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AMS Verification and Regression Testing of SoC Designs

AMS Verification and Regression Testing of SoC Designs
by Daniel Payne on 03-25-2014 at 10:02 am
Categories: EDA, Synopsys

Digital verification engineers on SoC designs have adopted many techniques to help ensure first silicon success: using compiled simulators, constrained random test, simulation farms, SystemVerilog methodology, and self-checking testbenches. AMS verification has tended to be ad-hoc or sharply divided into separate analog… Read More

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Imagine what all the DLP technology can do for you

Imagine what all the DLP technology can do for you
by Pawan Fangaria on 03-24-2014 at 7:00 pm
Categories: EDA, Foundries

Light has become integral part of most of the electronic devices we use today in any sphere of influence; personal, entertainment, consumer, automotive, medical, security, and industrial and so on. It’s obvious; along with IoT (Internet-of-Things) devices, the devices to illuminate and display things will play a major role… Read More

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IC Implementation Tool Gets a Rewrite, Now 10X Faster

IC Implementation Tool Gets a Rewrite, Now 10X Faster
by Daniel Payne on 03-24-2014 at 10:05 am
Categories: EDA, Synopsys

EDA start-up companies often have the advantage over established vendors by being able to start from scratch, instead of having to maintain some legacy code that no longer is competitive. But what happens when the established vendor decides to rewrite their IC implementation tools from scratch? In this case it’s good news,… Read More

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How Students Can Attend DAC for Free

How Students Can Attend DAC for Free
by Daniel Payne on 03-23-2014 at 11:29 am
Categories: EDA, Events

The annual Design Automation Conference (DAC) is a big deal and should be of interest to students considering a career in developing software to help automate some of the toughest design and verification challenges in SoC design. Maybe the cost of attending and traveling to DAC is an issue for you. The organizers of DAC are continuing… Read More

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The CAD Team – Unsung Heroes in a Successful Tapeout

The CAD Team – Unsung Heroes in a Successful Tapeout
by Daniel Nenni on 03-23-2014 at 11:00 am
Categories: Cliosoft, EDA

For most of my career, I worked as a CAD and design flow engineer. In the fall of 2012, I moved to a different role, as an applications and support manager at ClioSoft Inc. In my opinion, this was a very good opportunity for me to work with other CAD engineers and teams.

Having worked with different CAD teams in my career, I have often felt… Read More