I must admit. I was too comfortable. Let me explain, I’m a ModelSim guy from Mentor Graphics. I did not really think nor care much of the other RTL simulator options. How could someone build a better tool with respect to simulation? Let me introduce you to Aldec. Aldec was founded in 1984 by Dr. Stanley M. Hyduke. 30 years later they are… Read More
Electronic Design Automation
Just Released! Fabless: The Transformation of the Semiconductor Industry
The book “Fabless: The Transformation of the Semiconductor Industry” is now available in the Kindle (mobi) and iBooks (ePub) formats. We are really looking forward to your feedback before we go to print in March. This was truly a Tom Sawyer experience for me. As the story goes Tom made whitewashing a fence seem like fun so his friends… Read More
A Power Optimization Flow at the RTL Design Stage
SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all… Read More
Semiconductor IP and Correct-by-construction Workspaces
SoC hardware designers could learn a thing or two from the world of software development, especially when it comes to the topic of managing complexity. Does that mean that hardware designers should literally use a software development environment, and force fit hardware design into file and class-based software methodologies?… Read More
Smart Clock Gating for Meaningful Power Saving
Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More
Digital @ Nano-Scale while Analog Hovers @ 65nm and Above
Who’s going to DesignCon next week? I am, absolutely. Dr. Hermann Eul, Vice President & General Manager, Mobile & Communications Group, Intel Corporation will be keynoting on Tuesday. This one I want to hear! Intel missed mobile at 32nm, 22nm, and 14nm. Lets see what they have planned for 10nm. Something good I hope!… Read More
The Semiconductor Landscape – III
In continuation to my earlier observations and anticipations (landscape1, landscape2) which came up to my expectations, I was further inspired to ponder over the macros of our ever growing semiconductor industry. We may argue the business is stagnating, we may argue that the pace of scaling is slowing, but when I look back at the… Read More
Managing Heat for System Reliability
In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue… Read More
JasperGold COV App, the Swiss Army Knife for Verification
At the Jasper Users Group meeting in October Rajeev Ranjan presented on the JasperGold COV App which he described as the Swiss army knife for verification. It comes in many sizes and contains many useful tools.
The primary goal of COV is to provide coverage metrics:
- stimuli coverage: how restrictive is the design behavior under
Positive Semiconductor Job Outlook in 2014!
Based on local traffic patterns and my experience in Silicon Valley over the last 30 years we are looking at a much higher employment rate inside the fabless semiconductor ecosystem, absolutely. Jobs are being filled more so than I have seen in the past ten years. The challenge of course is finding the right people for the right job… Read More
Should Intel be Split in Half?