In today’s era of low power and high performance components, preferably on a single chip provides impetus to much larger electronic systems packaged into much smaller cases; smartphones are the immediate examples which encapsulate multiple functions other than the intended ones, viz. phone and data communication. As an example,… Read More
Electronic Design Automation
EDA Mergers & Acquisitions Wiki Now Includes IP
When I started collecting my list of EDA mergers and acquisitions about 30 years ago, my objective was simply to determine the number of logos each EDA company owns. For that reason, I collected all the fish-eat-fish-eat-fish…. mergers and acquisitions, going way back to the very early days of EDA (even before it was called EDA).… Read More
Modeling and Analysis of Single Event Effects (SEE)
Single Event Effects (SEE) are important because we depend upon our consumer, industrial and aerospace products to work reliably. Protons, electrons, neutrons, or alpha particles may perturb the MOS or bipolar device operation in either a destructive or non-destructive fashion. Galactic cosmic rays are one source of these… Read More
S-engine Moves up the Integration of IPs into SoCs
As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and… Read More
Coventor Brings More Accuracy & Performance into Design of MEMS Devices
Although MEMS devices in various forms are now found in most electronic devices, predominantly in mobile, automotive, aerospace and many other applications, their major revolution, I believe, is yet to happen. We are seeing rapid innovation in MEMS reflected by their improvements in precision, performance, size reduction,… Read More
An Approach to Clock Domain Crossing for SoC Designs
Blogger Pawan Fangaria wrote about Clock Domain Crossing(CDC) a few weeks ago, and so I followed up tonight and watched a webinarabout CDC presented by Ravindra Anejaof Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:
- Fast throughput and thoroughness
- Ability to debug and fix the source
In Case You Missed #51DAC
This will probably end up being the most memorable DAC for us since Paul and I signed hundreds of copies of our book “Fabless: The Transformation of the Semiconductor Industry”. I’m not sure how we are going to top that next year but I’m confident we will think of something. If you want to catch up on the live blogs from the last three conferences… Read More
So Easy To Learn VIP Integration into UVM Environment
It goes without saying that VIPs really play a Very Important Part in SoC verification today. It has created a significant semiconductor market segment in the fabless world of SoC and IP design & verification. In order to meet the aggressive time-to-market for IPs and SoCs, it’s imperative that readymade VIPs which are proven… Read More
Analog FastSPICE Update at DAC
Tuesday night over dinner at DAC I was able to chat with Ravi Subramanian, CEO of Berkeley DA, recently acquired by Mentor Graphics back on March 21st. This acquisition provided Mentor with an Analog FastSPICE circuit simulator to round out its collection of simulators.… Read More
PCI Express 4 specification just released for PCI-SIG DevCon
I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members’ review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP… Read More


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