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EDA

Electronic Design Automation

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Logic Synthesis Reborn

Logic Synthesis Reborn
by Daniel Payne on 06-03-2015 at 9:45 am
Categories: Cadence, EDA

Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write … Read More

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Even More Integration and Automation for ARM-based Designs

Even More Integration and Automation for ARM-based Designs
by Daniel Payne on 06-03-2015 at 8:00 am
Categories: Arm, EDA

The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying … Read More

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Making Things Visible for 25 Years

Making Things Visible for 25 Years
by Paul McLellan on 06-03-2015 at 7:00 am
Categories: Concept Engineering, EDA

This year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development groups in semiconductor… Read More

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A Robust Lint Methodology Ensures Faster Design Closure

A Robust Lint Methodology Ensures Faster Design Closure
by Pawan Fangaria on 06-03-2015 at 4:00 am
Categories: EDA

With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different… Read More

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Aldec packs 6 UltraScale parts on HES-7

Aldec packs 6 UltraScale parts on HES-7
by Don Dingee on 06-01-2015 at 12:00 pm
Categories: Aldec, EDA, FPGA

A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”,… Read More

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Will those IO pad rings pass foundry muster?

Will those IO pad rings pass foundry muster?
by Beth Martin on 05-31-2015 at 10:00 pm
Categories: EDA, Siemens EDA

I was talking recently to Dina Medhat, a senior technical marketing engineer at Mentor, about, of all things, IO rings. It has not occurred to me that verifying that your IO rings comply with foundry rules presents new challenges.

IO ring checking isn’t new, nor is it unique to advanced IC process nodes. However, the same forces of… Read More

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NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile

NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile
by Daniel Payne on 05-31-2015 at 4:00 pm
Categories: EDA

Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors… Read More

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Atmel Tightens Automotive Focus with Three New Cortex-M7 MCUs

Atmel Tightens Automotive Focus with Three New Cortex-M7 MCUs
by Majeed Ahmad on 05-31-2015 at 11:30 am
Categories: Arm, EDA, IoT, IP

Atmel Corp., a lead partner for the ARM Cortex-M7 processor launch in October 2014, has unveiled three new M7-based microcontrollers with a unique memory architecture and advanced connectivity features for the connected car market.

According to the company spokesman, E70, V71 and V70 chips are the industry’s highest performing… Read More

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Changing Trends at the Top of Semicon Space

Changing Trends at the Top of Semicon Space
by Pawan Fangaria on 05-31-2015 at 5:00 am
Categories: EDA, Foundries

As we have moved down from a CAGR of ~9% over last three decades to a CAGR of ~5% in the current decade, it’s time to check the realities. It can be definitely argued that a 5% of CAGR over a solid base of ~$378 billion should be considered good enough. In my view that’s the sign of maturity in the semiconductor market. At the same time we are… Read More

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Semiconductor Acquisitions will Fuel Innovation!

Semiconductor Acquisitions will Fuel Innovation!
by Daniel Nenni on 05-30-2015 at 7:00 am
Categories: EDA, eSilicon, Foundries, IP

Has the semiconductor world gone acquisition crazy? It certainly seems that way with the more than $60B in M&A activity which may now include Altera. We are probably getting close to the 80/20 rule where 80% of the semiconductor revenue is being generated by 20% of the companies. Not far off from where we were at 25 years ago when… Read More