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WP_Term Object
(
[term_id] => 157
[name] => EDA
[slug] => eda
[term_group] => 0
[term_taxonomy_id] => 157
[taxonomy] => category
[description] => Electronic Design Automation
[parent] => 0
[count] => 4197
[filter] => raw
[cat_ID] => 157
[category_count] => 4197
[category_description] => Electronic Design Automation
[cat_name] => EDA
[category_nicename] => eda
[category_parent] => 0
[is_post] =>
)
IoT or wearable: it’s fascinating to see how many articles, blogs, and comments have been posted about them during the last two years! IoT business potential is huge as are the number of possible applications. If we summarize the functions within a wearable system we can count:
[LIST=1]
CPU: it can be a standard Microcontroller …
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Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write … Read More
The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying … Read More
This year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development groups in semiconductor… Read More
With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different… Read More
A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”,… Read More
I was talking recently to Dina Medhat, a senior technical marketing engineer at Mentor, about, of all things, IO rings. It has not occurred to me that verifying that your IO rings comply with foundry rules presents new challenges.
IO ring checking isn’t new, nor is it unique to advanced IC process nodes. However, the same forces of… Read More
Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors… Read More
Atmel Corp., a lead partner for the ARM Cortex-M7 processor launch in October 2014, has unveiled three new M7-based microcontrollers with a unique memory architecture and advanced connectivity features for the connected car market.
According to the company spokesman, E70, V71 and V70 chips are the industry’s highest performing… Read More
As we have moved down from a CAGR of ~9% over last three decades to a CAGR of ~5% in the current decade, it’s time to check the realities. It can be definitely argued that a 5% of CAGR over a solid base of ~$378 billion should be considered good enough. In my view that’s the sign of maturity in the semiconductor market. At the same time we are… Read More
Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside