Synopsys IP Designs Edge AI 800x100
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EDA

Electronic Design Automation

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12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers

12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
by Daniel Payne on 10-07-2015 at 7:00 am
Categories: EDA, MunEDA

My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More

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A FinFET BSIM-CMG model update from UC-Berkeley

A FinFET BSIM-CMG model update from UC-Berkeley
by Tom Dillinger on 10-06-2015 at 4:00 pm
Categories: EDA

Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php… Read More

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Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am
Categories: EDA, IP, Semiconductor Services

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More

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Solidly Across the Chasm

Solidly Across the Chasm
by Paul McLellan on 10-05-2015 at 12:00 pm
Categories: EDA, Solido

Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?

See also Getting EDA Across the Chasm: 15 Rules Before and 5 After

The founding team of Solido:

  • discovered process variation for analog was a problem as companies
… Read More
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Something Old, Something New…EDA and Verification

Something Old, Something New…EDA and Verification
by Ellie Burns on 10-04-2015 at 12:00 pm
Categories: EDA, Siemens EDA

When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should … Read More

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Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes

Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
by Pawan Fangaria on 10-04-2015 at 7:00 am
Categories: EDA, Synopsys

There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology … Read More

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What’s Testing Design Limits at ITC?

What’s Testing Design Limits at ITC?
by Beth Martin on 10-02-2015 at 12:00 pm
Categories: EDA, Siemens EDA

The 46[SUP]th[/SUP] IEEE International Test Conference (ITC) will be held the week of October 5, 2015 at the Disneyland Hotel Conference Center in Anaheim, California. ITC is where you will discover the latest ideas and learn about practical applications of test technologies.

As you take in panels, tutorials, presentations,… Read More

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Getting EDA Across the Chasm: 15 Rules Before and 5 After

Getting EDA Across the Chasm: 15 Rules Before and 5 After
by Paul McLellan on 10-02-2015 at 7:00 am
Categories: EDA, Solido

Crossing the Chasm by Geoffrey Moore (not that G. Moore!) is one of the most well known books on high technology marketing. When I worked at VaST, Mohr Davidow Ventures (MDV) invested in us and Moore (not Mohr), who was a partner there, spent an afternoon with us brainstorming what it would take for us to cross the chasm. Coincidentally,… Read More

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Top 10 Reasons to invest in Interactive Design Rule Checking tools

Top 10 Reasons to invest in Interactive Design Rule Checking tools
by Tom Dillinger on 10-01-2015 at 12:00 pm
Categories: EDA, Siemens EDA

One of the most energetic presentations at the recent TSMC OIP 2015 symposium was given by Tom Williams from Qualcomm, who shared his insights (and enthusiasm!) for Mentor’s Calibre RealTime interactive Design Rule Checking (iDRC) product.

Paraphrasing Tom’s presentation (and with a tip of the hat to David Letterman), here … Read More

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EDA By the Numbers, Phil Kaufman, Emerging Companies and More

EDA By the Numbers, Phil Kaufman, Emerging Companies and More
by Paul McLellan on 10-01-2015 at 7:00 am
Categories: EDA, Events, IP

The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior… Read More