Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Electrical-Optical Design, A Bridge to Terabitsia

Electrical-Optical Design, A Bridge to Terabitsia
by Mitch Heins on 07-19-2016 at 12:00 pm

If you don’t get the tongue in cheek reference of the title, you probably don’t have children who liked to watch Disney movies. All four of my daughters loved Disney and so, I am forever shaped by the Wonderful World of Disney. In 2007 Disney adapted to the screen a novel called, ‘A Bridge to Terabithia’, in which two adolescents escape… Read More


10 Challenges in IP Design Collaboration

10 Challenges in IP Design Collaboration
by Don Dingee on 07-18-2016 at 4:00 pm

Enterprise design management can be summed up in one word: collaboration. Intellectual property (IP) reuse and the success of distributed system-on-chip (SoC) design efforts depend strongly on how well designers can collaborate. As time-to-market windows have shortened, the challenges around design collaboration have… Read More


Integrity and Reliability in Analog and Mixed-Signal

Integrity and Reliability in Analog and Mixed-Signal
by Bernard Murphy on 07-18-2016 at 1:30 pm

In the largest and fastest growing categories in electronics – mobile, IoT and automotive – analog is playing an increasingly important role. It’s important in delivering high integrity power and critical signals to the design though LDO regulators and PLLs, in managing high speed interfaces like DDR and SERDES, in interfacing… Read More


New Transistor Sizing Company at #53DAC

New Transistor Sizing Company at #53DAC
by Daniel Payne on 07-18-2016 at 12:00 pm

I first met Herve Guegan at Mentor Graphics back in the late 90’s when he managed a group of developers for the SPICE circuit simulator called Eldo in Grenoble, France. We’ve kept in touch over the years and he asked to meet me at DAC in Austin this year, so I caught up with him to get an update on his latest start-up company… Read More


IC and System Design for Mobile and Wearable Devices!

IC and System Design for Mobile and Wearable Devices!
by Daniel Nenni on 07-16-2016 at 7:00 am

The Linley Mobile and Wearable Conference is coming up so let’s take a look at what is in store for us. Bernard Murphy, Tom Simon, and I will be covering the event live for SemiWiki and we will also be doing a book giveaway/signing for our new “Prototypical” book (compliments of S2C Inc.) during the networking event on Tuesday evening.… Read More


Webinar alert – Hybrid prototyping for ARMv8

Webinar alert – Hybrid prototyping for ARMv8
by Don Dingee on 07-15-2016 at 4:00 pm

All the talk about ARM server SoCs has been focused on who will come up with the breakthrough chip design. Watching trends like OPNFV develop suggests the big breakthrough is more likely to come on the ARMv8 software side. How do you quickly validate ARMv8 software when you don’t have the exact ARMv8 SoC target?… Read More


Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar

Learn How to Debug UVM Test Benches Faster – Upcoming Synopsys Webinar
by Bernard Murphy on 07-14-2016 at 4:00 pm

UVM for developing testbenches is a wonderful thing, as most verification engineers will attest. It provides abstraction capabilities, it encapsulates powerful operations, it simplifies and unifies constrained-random testing – it has really revolutionized the way we verify at the block and subsystem level.

However great… Read More


5 Reasons Why Platform Based Design Can Help Your Next SoC

5 Reasons Why Platform Based Design Can Help Your Next SoC
by Daniel Payne on 07-14-2016 at 12:00 pm

Semiconductor design IP and verification IP have been around for decades, but just because your company has lots of IP doesn’t mean that you’re getting all of the benefits of a design reuse methodology. Maybe your business has encountered some of the following issues:

Read More

EDA Tool for ATPG – Refactor or Rewrite?

EDA Tool for ATPG – Refactor or Rewrite?
by Daniel Payne on 07-12-2016 at 3:00 pm

In the life of all EDA software tools comes that moment when new requirements make developers stop and ask, should I continue to refactor the existing code or just start all over from scratch using a new approach? Synopsys came to that junction point when ATPG run times were reaching days or even weeks on the largest IC designs, something… Read More