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Webinar: Multiphysics Reliability Signoff for Next-Generation Automotive Electronics Systems

Webinar: Multiphysics Reliability Signoff for Next-Generation Automotive Electronics Systems
by Bernard Murphy on 02-08-2018 at 7:00 am

In case you missed the TSMC event, ANSYS and TSMC are going to reprise a very important topic – signing-off reliability for ADAS and semi-autonomous /autonomous systems. This topic hasn’t had a lot of media attention amid the glamor and glitz of what might be possible in driverless cars. But it now seems like the cold light of real … Read More


Machine Learning And Design Into 2018 – A Quick Recap

Machine Learning And Design Into 2018 – A Quick Recap
by Alex Tan on 02-07-2018 at 3:00 pm

How could we differentiate between deep learning and machine learning as there are many ways of describing them? A simple definition of these software terms can be found here. Let’s look into Artificial Intelligence (AI), which was coined back in 1956. The term AI can be defined as human intelligence exhibited by machines.Read More


Is there anything in VLSI layout other than “pushing polygons”? (6)

Is there anything in VLSI layout other than “pushing polygons”? (6)
by Dan Clein on 02-05-2018 at 12:00 pm

I am very sorry but I have to break the flow of sharing initiatives, to reiterate the reason for these articles and maybe amplify the message these articles should promote.

I got a few inquiries from LinkedIn connections, who read the previous articles, with a very interesting point of view. This proves that after 5 articles some … Read More


In-System Automotive Test

In-System Automotive Test
by Daniel Payne on 02-01-2018 at 12:00 pm

I’ve been driving cars since 1975 and in the early days we had simplistic gauges for feedback like: Speed, Fuel level, Oil level, RPM. Back then when you popped the hood of a car you could see through the engine compartment onto the ground below, however with today’s cars the engine compartments are crammed with tubes,… Read More


Crystal Bulb: Sharing Design Intelligence

Crystal Bulb: Sharing Design Intelligence
by Bernard Murphy on 02-01-2018 at 7:00 am

There is a trend among design companies to want to extract more intelligence, from designs in-process and designs past, in support of optimizing total enterprise efficiency. Design automation companies see opportunity in leveraging this interest since they, in various ways, have a handle on at least part of the underlying data.… Read More


Automotive Mega-trends, Safety and Requirements Management

Automotive Mega-trends, Safety and Requirements Management
by Daniel Payne on 01-30-2018 at 12:00 pm

I come from a car-centric family where my father actually bought and sold over 300 vehicles in his lifetime, so automotive mega-trends pique my interest. A new conference called Semiconductors ISO 26262 held it’s first annual event last month, meeting in Munich with guest speakers from some impressive companies like: … Read More


Conflating ISO 26262 and DO-254

Conflating ISO 26262 and DO-254
by Bernard Murphy on 01-30-2018 at 7:00 am

If you’re in the ASIC business, by now you should have a rough understanding of ISO 26262, the safety standard for automotive electronics. You may be less familiar with DO-254 which has somewhat similar intent for airborne electronics. Unless, that is, you design with FPGAs in which case your familiarity may be the other way around… Read More


IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow

IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow
by Mitch Heins on 01-29-2018 at 12:00 pm

Until recently, ICs at bleeding edge nodes like 7nm technology from foundries like TSMC were mostly targeted for high-performance-computing (HPC) and mobile applications or possibly high radix switches that needed the increased performance of advanced nodes. The momentum of Moore’s law and Moore-than-Moore saw foundries… Read More


Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register… Read More


Designing an SoC for 3D TV Without using the Funny Glasses

Designing an SoC for 3D TV Without using the Funny Glasses
by Daniel Payne on 01-24-2018 at 12:00 pm

In the blur of activities at DAC last year I visited the Mentor booth a few times and had just a few minutes to glance at a 3D TV display that didn’t require me to wear any funny glasses, kind of novel I thought at the time because I’ve read that the market of 3D TV sets is being hampered by requiring viewers to wear glasses. The… Read More