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WP_Term Object
(
[term_id] => 157
[name] => EDA
[slug] => eda
[term_group] => 0
[term_taxonomy_id] => 157
[taxonomy] => category
[description] => Electronic Design Automation
[parent] => 0
[count] => 4439
[filter] => raw
[cat_ID] => 157
[category_count] => 4439
[category_description] => Electronic Design Automation
[cat_name] => EDA
[category_nicename] => eda
[category_parent] => 0
[is_post] =>
)
This area of automating the design of Flat Panel Displays (FPD) is so broad that it has taken me three blogs to cover all of the details, so in brief review the first two blogs were:
My final blog covers five areas:
- DRC/LVS for curvilinear layout
- Circuit
…
Read More
What Might the “1nm Node” Look Like?by Tom Dillinger on 12-28-2020 at 6:00 amCategories: EDA, Events, Synopsys
The device roadmap for the next few advanced process nodes seems relatively clear. The FinFET topology will subsequently be displaced by a “gate-all-around” device, typically using multiple stacked channels with a metal gate completely surrounding the “nanosheets”. Whereas the fin demonstrates improved gate-to-channel… Read More
A quick Q&A with Jeff Hancock, senior product manager for Mentor Embedded Platform Solutions, Siemens Digital Industries Software. Jeff oversees the Nucleus® real-time operating system (RTOS) and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services. Over the… Read More
In my prior post on NetApp, I discussed how the company’s FlexCache technology can keep distributed design teams in sync. Coordination and collaboration are critical elements of any complex design project. The ability to deliver results quickly while managing the massive amounts of data is also a critical element of success.… Read More
Last month, I blogged about a webinar on embedded systems development presented by Agnisys CEO and founder Anupam Bakshi. I liked the way that he linked their various tools into a common flow that spans hardware, software, design, verification, validation, and documentation. Initially I was rather focused on the design aspects… Read More
You might think that cloud services run on never-ending racks of servers and switches in giant datacenters. But what they really run on is trust. Trust that your data (or your client’s data) is absolutely tamper-proof inside that datacenter. Significantly more secure than it would be if you tried to manage the same operations in… Read More
As regular readers may know, every few months I check in with Cristian Amitroaie, CEO of AMIQ EDA, to see what’s new with the company and their products. In our posts so far this year we’ve focused on verification, and now I’m wondering how an integrated development environment (IDE) provides benefits to designers. They work on huge… Read More
The Cadence Virtuoso Design System has been one of the premier Integrated Circuit design systems for many years and is used by most major semiconductor companies. While it is powerful and versatile, it is often not optimized for certain complex, repetitive and time-consuming layout design tasks.
The founder and president … Read More
Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a host and device is required. A consortium to enable this new standard is in place, and a lot of heavy hitters are behind the standard, including … Read More
‘Tis the season, a time when a lot of companies summarize the year, send out holiday greetings and generally wind down until after the New Year. That’s not the case at Cliosoft. Their marketing machine has been in full gear with lots of new, useful and compelling content. I’ll provide a round-up of what’s happening. You can close… Read More
Silicon Insurance: Why eFPGA is Cheaper Than a Respin — and Why It Matters in the Intel 18A Era