wide 1
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4185
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4185
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More


Cadence Dives Deeper at Linley Fall Processor Conference

Cadence Dives Deeper at Linley Fall Processor Conference
by Randy Smith on 11-05-2019 at 10:00 am

I wrote about Cadence AI IP not long ago when I covered the Cadence Automotive Summit at the end of July (Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving, Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear). One of those two blogs remains one of my most widely … Read More


New ARC VPX DSP IP provides parallel processing punch

New ARC VPX DSP IP provides parallel processing punch
by Tom Simon on 10-29-2019 at 6:00 am

The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development… Read More


Cadence Shows off 5LPE Hercules Implementation

Cadence Shows off 5LPE Hercules Implementation
by Randy Smith on 10-28-2019 at 10:00 am

In a joint presentation given by Samsung, Arm, and Cadence at the Arm TechCon event on October 9, 2019, Cadence showed some results and explained its collaboration project used to implement the new Arm Hercules CPU on Samsung’s advanced 5LPE process. I do not want to minimize the significance of Samsung’s and Arm’s participation… Read More


DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am

57DAC in SFO

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More


IP-XACT helps you produce exactly what you need in SoC deliverables

IP-XACT helps you produce exactly what you need in SoC deliverables
by Tom Simon on 10-24-2019 at 10:00 am

If you have ever watched an experienced glass blower, your first thought is that they make it look so easy. I have had the opportunity to blow glass, and I can tell you that it is a constant struggle against temperature, time and muscles to get the glass to do anything like what you want. This is akin to what is required to take the elements… Read More


Accelerating Functional Safety Verification

Accelerating Functional Safety Verification
by Bernard Murphy on 10-24-2019 at 6:00 am

FuSa Verification

Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or … Read More


WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for… Read More


Statistically speaking you probably care about On-chip Variation

Statistically speaking you probably care about On-chip Variation
by admin on 10-22-2019 at 10:00 am

There are some metaphorical similarities between reaching timing signoff and driving a car to your destination. Most of us get in the car, turn the key and push the gas pedal to make it go. While we might have a cursory understanding of what makes it go, there are actually a lot of “moving part” under the hood in each instance. For most… Read More


WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior

WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior
by Daniel Nenni on 10-21-2019 at 6:00 am

Siemens Mentor recently announced PAVE360™, a very cool comprehensive pre silicon simulation environment. Autonomous cars are very popular here in Silicon Valley and quite safe on the highways since the average speed is 25mph (horrible traffic). In the city you need autonomous parking unless you want to waste precious time … Read More