Banner 800x100 0810
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4237
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4237
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

The Practitioners View of DAC – Design, IP and Embedded

The Practitioners View of DAC – Design, IP and Embedded
by Mike Gianfagna on 12-07-2020 at 10:00 am

The First DAC

Next year will mark the 58th year for the Design Automation Conference. It’s hard to wrap your head around the fact this event dates back to 1964, when rock ‘n roll was new, cars were big and computers were even bigger. In its early days, the event was called the Design Automation Workshop. Pictured above is the cover of the very first… Read More


Curvilinear FPD Layout and Schematics

Curvilinear FPD Layout and Schematics
by Daniel Payne on 12-03-2020 at 10:00 am

layout ladder min

You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:

What follows is the second part of a Q&A discussion with Chen Zhao… Read More


A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


ML plus formal for analog. Innovation in Verification

ML plus formal for analog. Innovation in Verification
by Bernard Murphy on 11-30-2020 at 6:00 am

innovation min

Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.

The Innovation

This month’s pick… Read More


Cadence is Making Floorplanning Easier by Changing the Rules

Cadence is Making Floorplanning Easier by Changing the Rules
by Mike Gianfagna on 11-25-2020 at 8:00 am

Mixed placement floorplan

SoC designs are getting more complex, resulting in a higher level of difficulty to get anything done. This trend is well-known. What I want to focus on here is how to deal with the issue of complexity. There are many approaches to taming this problem — faster algorithms for one, and improved algorithm efficiency or the ability to run… Read More


EDA Tool Support for GAA Process Designs

EDA Tool Support for GAA Process Designs
by Daniel Nenni on 11-23-2020 at 6:00 am

GAA FinFET

With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.

I will talk… Read More


The Impact of AI-enabled EDA Tools on the Semiconductor Industry

The Impact of AI-enabled EDA Tools on the Semiconductor Industry
by Richard Wawrzyniak on 11-22-2020 at 10:00 am

AI Tools Blog 111820

The semiconductor industry today is faced with several substantial issues—the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has … Read More


The Six Signs That You Need a Yield Management System

The Six Signs That You Need a Yield Management System
by Mike Gianfagna on 11-18-2020 at 6:00 am

The Six Signs That You Need a Yield Management System

If you search on “the six signs” you will find references to a fantasy novel, “The Dark is Rising Sequence” by Susan Cooper. In this fantasy work there are six signs: wood, bronze, iron, water, fire and stone. Their purpose has something to do with driving away the Dark. Here is a quote from the book that puts these six signs in some context:… Read More


Third Generation of IP Lifecycle Management Launched

Third Generation of IP Lifecycle Management Launched
by Daniel Payne on 11-17-2020 at 10:00 am

Methodics and Perforce

Back in July I first read the news that Perforce had acquired Methodics, and wasn’t too surprised, because many of the EDA vendors that we blog about do get acquired or merge with similar sized companies in order to be part of a bigger offering. When Methodics announced a webinar introducing IPLM 3.0 (IP Lifecycle Management),… Read More


The History and Significance of Power Optimization, According to Jim Hogan

The History and Significance of Power Optimization, According to Jim Hogan
by Mike Gianfagna on 11-13-2020 at 10:00 am

Jim Hogan

Power seems to be on everyone’s mind these days. Hyperscale data centers worry about operating costs unless power is optimized. The AI accelerators in the Edge can’t be effective without optimized power. Advanced 2.5 and 3D packages simply can’t remove the heat unless power is optimized.  And then there’s all those gadgets we … Read More