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Upcoming Virtual Event: Designing a Time Interleaved ADC for 5G V2X Automotive Applications

Upcoming Virtual Event: Designing a Time Interleaved ADC for 5G V2X Automotive Applications
by Kalar Rajendiran on 08-03-2021 at 10:00 am

Mohammed Ismail Wayne State University

Over the last decade or so, the automotive industry has been rapidly adopting and deploying innovative and revolutionary technologies in automobiles. One such revolution is the autonomous vehicle technology. While this technology is not fully mature yet, some components of this technology are. Many late model automobiles… Read More


Prototypical II PDF is now available!

Prototypical II PDF is now available!
by Daniel Nenni on 08-02-2021 at 6:00 am

Prototypical II

Our latest book has finally been published! A PDF version of “Prototypical II – The Practice of FPGA Prototyping for SoC Design” is now available in the SemiWiki book section. The first book “Prototypical – The Emergence of FPGA Prototyping for SoC Design” was published in 2016 and a lot … Read More


Podcast EP31: Interview with Dr. Rosemary Francis, Chief Scientist at Altair

Podcast EP31: Interview with Dr. Rosemary Francis, Chief Scientist at Altair
by Daniel Nenni on 07-30-2021 at 10:00 am

Dan is joined by Dr. Rosemary Francis. Rosemary was the managing director and CEO of Ellexus Ltd. before its acquisition by Altair. Dan explores the I/O profiling technology Ellexus brought to Altair, it’s impact and the implications for the future. A behind-the-scenes view of the acquisition is also provided.

Dr. Rosemary… Read More


Cerebrus, the ML-based Intelligent Chip Explorer from Cadence

Cerebrus, the ML-based Intelligent Chip Explorer from Cadence
by Kalar Rajendiran on 07-29-2021 at 10:00 am

Screen Shot 2021 07 21 at 4.39.06 PM

Electronic design automation (EDA) has come a long way from its beginnings. It has enabled chip engineers from specifying designs directly in layout format during the early days to today’s capture in RTL format. Every advance in EDA has made the task of designing a chip easier and increased the design team productivity, enabling… Read More


SoC Vulnerabilities

SoC Vulnerabilities
by Daniel Payne on 07-29-2021 at 6:00 am

side channel attack

As I read both the popular and technical press each week I often see articles about computer systems being hacked, and here’s just a few vulnerabilities from this week:

Read More

Optimize RTL and Software with Fast Power Verification Results for Billion-Gate Designs

Optimize RTL and Software with Fast Power Verification Results for Billion-Gate Designs
by Johannes Stahl on 07-28-2021 at 10:00 am

ZeBu Empower diagram

In every chip, power is a progressive problem to be solved. Designers have long had to rely on a combination of experience and knowledge to tackle this dilemma, typically having to wait until after silicon availability to perform power analysis with realistic software workloads. However, this is too late in the game, as it becomes… Read More


Instrumenting Post-Silicon Validation. Innovation in Verification

Instrumenting Post-Silicon Validation. Innovation in Verification
by Bernard Murphy on 07-28-2021 at 6:00 am

Instrumenting Post-Silicon Validation

Instrumenting post-silicon validation is not a new idea but here’s a twist. Using (pre-silicon) emulation to choose debug observation structures to instrument in-silicon. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research… Read More


EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


A Custom Layout Environment for SOC Design Closure

A Custom Layout Environment for SOC Design Closure
by Tom Simon on 07-22-2021 at 10:00 am

custom layout environment

Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement… Read More