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Synopsys Enhances Chips and Systems with New Silicon Lifecycle Management Platform

Synopsys Enhances Chips and Systems with New Silicon Lifecycle Management Platform
by Mike Gianfagna on 10-26-2020 at 6:00 am

Silicon Lfecycle Management

SLM.  It’s a TLA (three-letter acronym) that you’ll be hearing more about. It stands for silicon lifecycle management and it has the potential of re-defining the role of EDA in the entire electronics ecosystem. A working definition of SLM is “monitoring, analysis and optimization of semiconductor devices as they are designed,… Read More


Clarity 3D Transient Solver Speeds Up EMI/EMC Certification

Clarity 3D Transient Solver Speeds Up EMI/EMC Certification
by Tom Simon on 10-25-2020 at 8:00 am

Clarity 3D Transient Solver

Cadence made waves a while back with its innovative Clarity 3D Solver, a FEM solver for near field EM analysis. Now they are shaking things up with their new far field Clarity 3D Transient Solver. System level EMI and EMC analysis has often exceeded the limits of simulation tools, leading to expensive and time-consuming prototype… Read More


Synopsys Teams with IBM to Increase AI Compute Performance 1,000X by 2029

Synopsys Teams with IBM to Increase AI Compute Performance 1,000X by 2029
by Mike Gianfagna on 10-21-2020 at 7:30 am

Synopsys Teams with IBM to Increase AI Compute Performance 1000X by 2029

Anyone who frequents SemiWiki will likely know Moore’s Law. The prediction made by Gordon Moore over 50 years ago regarding the relentless increase in transistor density and reduction in cost has tracked well for a very, very long time. In recent years, there has been spirited discussion about the end of Moore’s Law. This is a discussion… Read More


The Most Interesting CEO in Semiconductors!

The Most Interesting CEO in Semiconductors!
by Daniel Nenni on 10-21-2020 at 6:00 am

GTC 2020 Lip Bu Tan

Hands down, without a doubt, the most interesting CEO in semiconductors is Lip-Bu Tan, founder of Walden Capitol and current CEO of Cadence Design Systems. If you want to talk about a man with a plan it’s Lip-Bu Tan.

Before we get into the fireside chat between Tom Caufield and Lip-Bu at the GTC 2020 Virtual event let’s do a quick biography:… Read More


Covering Configurable Systems. Innovation in Verification

Covering Configurable Systems. Innovation in Verification
by Bernard Murphy on 10-20-2020 at 6:00 am

innovation min

Covering configurable systems is a challenge. What’s a good strategy to pick a small subset of settings and still get high confidence in coverage? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas, here an idea from software testing which should also apply to hardware. Feel free… Read More


Webinar on Synopsys MIPI IP

Webinar on Synopsys MIPI IP
by Tom Simon on 10-19-2020 at 10:00 am

Synopsys MIPI IP

MIPI may have started out as a standard for mobile phones, but it has become very important for connecting cameras and displays in a wide range of other things such as cameras, computers, drones, VR glasses, IoT devices and cars. Along the way it has matured by adding important features to support new applications. Now when we talk… Read More


yieldHUB – Helping Semiconductor Companies be More Competitive

yieldHUB – Helping Semiconductor Companies be More Competitive
by Mike Gianfagna on 10-19-2020 at 6:00 am

yieldHUB webinar

The semiconductor industry is fiercely competitive. This is widely known by the SemiWiki community. When it comes to critical design parameters such as power, performance or area you’re either in the envelope that defines the market or you’re not a player. Yield management has a similar impact. Those who can stay ahead of the yield… Read More


Power in Test at RTL Defacto Shows the Way

Power in Test at RTL Defacto Shows the Way
by Bernard Murphy on 10-15-2020 at 6:00 am

scan chains crossing power domainspng

In the early days of Atrenta I met with Ralph Marlett, a distinguished test expert with many years of experience at Zuken and Recal Redac. He talked me into believing we could do meaningful static analysis for DFT-friendliness at RTL. His work with us really opened my eyes to the challenges that test groups face in integrating their… Read More


Randomization Fools Us Some of the Time

Randomization Fools Us Some of the Time
by Bernard Murphy on 10-13-2020 at 6:00 am

random min

Though hopefully not some of us all of the time. Randomization is a technique used in verification to improve coverage in testing. You develop tests you know you have to run, then you throw randomization on top of that to search around those starter tests, to explore possibilities you haven’t considered. Truly random tests are not… Read More


Tempus: Delivering Faster Timing Signoff with Optimal PPA

Tempus: Delivering Faster Timing Signoff with Optimal PPA
by Mike Gianfagna on 10-12-2020 at 10:00 am

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More