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Ansys Acquires Another!

Ansys Acquires Another!
by Daniel Nenni on 05-16-2023 at 4:00 pm

Diakopto logo

The headline is: Ansys Signs Definitive Agreement to Acquire Diakopto, Expands Multiphysics Simulation Portfolio for Semiconductor Designers. The acquisition complements Ansys’ existing signoff solutions and enables integrated circuit (IC) designers to detect problems earlier in the design flow.

Which is certainly… Read More


Gate Resistance in IC design flow

Gate Resistance in IC design flow
by Maxim Ershov on 05-03-2023 at 6:00 am

Figure1 9

MOSFET gate resistance is a very important parameter, determining many characteristics of MOSFETs and CMOS circuits, such as:

• Switching speed
• RC delay
• Fmax – maximum frequency of oscillations
• Gate (thermal) noise
• Series resistance and quality factor in MOS capacitors and varactors
• Switching speed and uniformity… Read More


Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?

Bizarre results for P2P resistance and current density (100x off) in on-chip ESD network simulations – why?
by Maxim Ershov on 12-12-2022 at 6:00 am

Fig 1

Resistance checks between ESD diode cells and pads or power clamps, and current density analysis for such current flows are commonly used for ESD networks verification [1]. When such simulations use standard post-layout netlists generated by parasitic extraction tools, the calculated resistances may be dramatically higher… Read More


Your Symmetric Layouts show Mismatches in SPICE Simulations. What’s going on?

Your Symmetric Layouts show Mismatches in SPICE Simulations. What’s going on?
by Maxim Ershov on 11-07-2022 at 6:00 am

Figure1 6

This Diakopto paper discusses for the first time, a new effect – a false electrical mismatch in post-layout simulations for perfectly symmetric nets. This effect is caused by the difference in distributions of parasitic coupling capacitors over the nodes of parasitic resistor networks, even for symmetric nets. This, in turn,… Read More


Fast EM/IR Analysis, a new EDA Category

Fast EM/IR Analysis, a new EDA Category
by Daniel Payne on 08-09-2022 at 6:00 am

IR Drop min

I’ve watched the SPICE market segment into multiple approaches, like: Classic SPICE, Parallel SPICE, FastSPICE and Analog FastSPICE. In a similar fashion the same thing just happened to EM/IR analysis, because after years of waiting we finally have a different approach to EM/IR analysis that works at the top-level of … Read More


CEO Interview: Maxim Ershov of Diakopto

CEO Interview: Maxim Ershov of Diakopto
by Daniel Nenni on 09-24-2021 at 4:00 am

Maxim Ershov

Maxim is a scientist, engineer, and entrepreneur. His expertise is in physics, mathematics, semiconductor devices, and EDA. Prior to co-founding Diakopto, Maxim worked at Apple’s SEG (Silicon Engineering Group), where he was responsible for parasitic extraction. Before Apple, he was CTO of Silicon Frontline Technology,… Read More