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Displaced but Looking to Add EDA Tools Skills?

Displaced but Looking to Add EDA Tools Skills?
by Daniel Payne on 09-21-2012 at 1:12 pm

In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training.… Read More


A Brief History of Cadence Design Systems

A Brief History of Cadence Design Systems
by Daniel Nenni on 09-01-2012 at 8:10 pm

EDA software for IC and system design became a commercial business in the early 1980s. In those days, 3 companies – Daisy Systems, Mentor Graphics, and Valid Logic Systems – dominated the emerging EDA industry. However, two small startups that emerged in the early 1980s grew rapidly and merged to form Cadence Design Systems in 1988.… Read More


Mixed-Signal Methodology Guide

Mixed-Signal Methodology Guide
by Daniel Payne on 08-29-2012 at 11:14 am

Last week I reviewed Chapter 1 in the new book: Mixed-Signal Methodology Guide, and today I finish up my review of Chapters 2 through 11. You can read the entire book chapter by chapter, or just jump directly to the chapters most related to your design role or project needs. With multiple authors I was impressed with the wide range of… Read More


Book Review: Mixed-Signal Methodology Guide

Book Review: Mixed-Signal Methodology Guide
by Daniel Payne on 08-23-2012 at 4:00 pm

Almost every SoC has multiple analog blocks so AMS methodology is an important topic to our growing electronics industry. Authored by Jess Chen (Qualcomm), Michael Henrie (Cliosoft), Monte Mar (Boeing) and Mladen Nizic (Cadence), the book is subtitled: Advanced Methodology for AMS IP and SoC Design, Verification and ImplementationRead More


Cadence at 20nm

Cadence at 20nm
by Paul McLellan on 08-21-2012 at 8:10 pm

Cadence has a new white paper out about the changes in IC design that are coming at 20nm. One thing is very clear: 20nm is not simply “more of the same”. All design, from basic standard cells up to huge SoCs has several new challenges to go along with all the old ones that we had at 45nm and 28nm.

I should emphasize that the paper… Read More


MemCon 2012: Cadence and Denali

MemCon 2012: Cadence and Denali
by Eric Esteve on 08-20-2012 at 7:00 am

I was very happy to see that Cadence has decided to hold MEMCON again in 2012, in Santa Clara on September 18[SUP]th[/SUP] . The session will start with “New Memory Technologies and Disruptions in the Ecosystem”from Martin Lund.

Martin is the recently (March this year) appointed Senior VP for the SoC Realization Group at cadence:… Read More


40 Billion Smaller Things On The Clock

40 Billion Smaller Things On The Clock
by Don Dingee on 08-15-2012 at 8:00 pm

Big processors get all the love, it seems. It’s natural, since they are highly complex beasts and need a lot of care and feeding in the EDA and fab cycle. But the law of large numbers is starting to shift energy in the direction of optimizing microcontrollers.

I mulled the math in my head for a while. In a world with 7 billion people and … Read More


Cadence Digital Flow

Cadence Digital Flow
by Paul McLellan on 08-01-2012 at 8:01 pm

Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.

One of the tools in the Cadence… Read More


Addressing the Nanometer Digital Design Challenges! (Webinars)

Addressing the Nanometer Digital Design Challenges! (Webinars)
by Daniel Nenni on 07-27-2012 at 7:30 pm

Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start. … Read More


Parasitic-Aware Design Flow with Virtuoso

Parasitic-Aware Design Flow with Virtuoso
by Daniel Payne on 07-27-2012 at 12:01 pm

I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More