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Signoff Summit: The Fastest Path to Design Signoff

Signoff Summit: The Fastest Path to Design Signoff
by Daniel Nenni on 11-13-2013 at 8:00 pm

Cadence’s Signoff Summit will be held next week, November 21 at Cadence in San Jose.

This is the first of a series of all-day Signoff Summits from Cadence that focus on the multiple facets of design signoff. This first summit will include keynote addresses plus sessions covering the multiple solution components that comprise… Read More


A New IC Power Integrity Tool

A New IC Power Integrity Tool
by Daniel Payne on 11-12-2013 at 7:00 am

In EDA we have come to expect that only small start-up companies create new tools, however a team at Cadencehas developed a new IC power integrity tool called Voltus from scratch. To learn more I spoke last week with KT Moore, a Group Director at Cadence. I’ve known KT for over a decade, and first met him when he was at Magma marketing… Read More


nVidia: Virtual Platform/Emulation Hybrid

nVidia: Virtual Platform/Emulation Hybrid
by Paul McLellan on 11-05-2013 at 11:57 am

I was the VP marketing at VaST Systems Technology and then at Virtutech. Both companies sold virtual platform technology which consisted of two parts:

  • an extremely fast processor emulation technology that actually worked by doing a binary translation of the target binary code (e.g. an ARM) into the native instruction set of the
Read More

ARM in Samsung 14nm FinFET

ARM in Samsung 14nm FinFET
by Paul McLellan on 10-30-2013 at 4:28 pm

I am at ARM TechCon today. One interesting presentation was made jointly between Samsung, Cadence and ARM themselves about developing physical libraries (ARM), a tool flow (Cadence) and test chips (Samsung). It was titled Samsung ARM and Cadence collaborate on the silicon-proven world first 14-nm FinFET Cortex-A7 ARM CPU and… Read More


Cadence’s Mixed-Signal Technology Summit

Cadence’s Mixed-Signal Technology Summit
by Randy Smith on 10-28-2013 at 1:45 am

On October 10, I attended another Cadence Summit, this one titled the Cadence Mixed-Signal Technology Summit. Recently, I had written about the Cadence Silicon Verification Summit. The verification event was the first of its kind, and I thought it had terrific content. Being more of a digital guy myself, I was unaware that Cadence… Read More


Putting the Ten in Tensilica

Putting the Ten in Tensilica
by Paul McLellan on 10-17-2013 at 3:55 pm

Chris Rowen of Cadence’s Tensilica announced the tenth generation of the Xtensa customizable processor at the Linley Microprocessor Conference yesterday. Chris was one of the founders of Tensilica…back in 1997. I believe that the first version was released in 1999. Over the years the Tensilica business changed.… Read More


Spectre from Cadence Goes FastSPICE

Spectre from Cadence Goes FastSPICE
by Daniel Payne on 10-09-2013 at 2:31 am

Transistor-level circuit designers have an insatiable appetite to run numerous SPICE circuit simulations in order to determine circuit speed, current and power across Process, Voltage and Temperature (PVT) conditions. Just look at the number of PVT corners increasing as the technology nodes go to 16nm:

The good news today … Read More


Cadence’s System-to-Silicon Verification Summit

Cadence’s System-to-Silicon Verification Summit
by Randy Smith on 10-06-2013 at 6:00 pm

At this year’s DAC, I spoke with several friends at Cadence. I got the distinct impression that something at Cadence had changed. There was a sense of pride and accomplishment that it seems to me had drifted away over the years. Now employees were speaking with true conviction about the accomplishments of the product development… Read More


Cadence Grows VIP Business – What’s New?

Cadence Grows VIP Business – What’s New?
by Pawan Fangaria on 10-04-2013 at 10:00 am

VIPs (Verification IPs) are really important in this complex world of SoCs which involve various IPs, interfaces and continuously evolving protocols and standards, thus making the task of verifying an overall system extremely challenging. And the verification must be done in minimum possible run-time and memory consumption.… Read More


A Mixed-Signal IC Summit in San Jose

A Mixed-Signal IC Summit in San Jose
by Daniel Payne on 10-03-2013 at 9:26 am

Analog and mixed-signal ICs are tougher to design and verify compared to digital, so if you want to learn more about best practices from actual AMS engineers then consider attending a summitthat is sponsored by Cadence Design Systems next Thursday, October 10th in San Jose from 8:00AM until 6:30PM.

They’ve lined up an interesting… Read More