Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 6435
    [name] => AI
    [slug] => artificial-intelligence
    [term_group] => 0
    [term_taxonomy_id] => 6435
    [taxonomy] => category
    [description] => Artificial Intelligence
    [parent] => 0
    [count] => 734
    [filter] => raw
    [cat_ID] => 6435
    [category_count] => 734
    [category_description] => Artificial Intelligence
    [cat_name] => AI
    [category_nicename] => artificial-intelligence
    [category_parent] => 0
    [is_post] => 
)

ML-Guided Model Abstraction. Innovation in Verification

ML-Guided Model Abstraction. Innovation in Verification
by Bernard Murphy on 11-29-2023 at 6:00 am

Innovation New

Formal methods offer completeness in proving functionality but are difficult to scale to system level without abstraction and cannot easily incorporate system aspects outside the logic world such as in cyber-physical systems (CPS). Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst,… Read More


Synopsys.ai Ups the AI Ante with Copilot

Synopsys.ai Ups the AI Ante with Copilot
by Bernard Murphy on 11-27-2023 at 10:00 am

Synopsys.ai Stack 111623

Last week Synopsys announced their next step in generative AI (GenAI) in Synopsys.ai Copilot based on a collaboration with Microsoft. This integrates Azure OpenAI together with existing Synopsys.ai GenAI capabilities to extend Copilot concepts to the EDA world. For those of you unfamiliar with Copilot, this is a development… Read More


Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing

Navigating Edge AI Architectures: Power Efficiency, Performance, and Future-Proofing
by Kalar Rajendiran on 11-21-2023 at 10:00 am

CEVA Comprehensive Edge AI Portfolio

The surge in Edge AI applications has propelled the need for architectures that balance performance, power efficiency, and flexibility. Architectural choices play a pivotal role in determining the success of AI processing at the edge, with trade-offs often necessary to meet the unique demands of diverse workloads. There are… Read More


Cadence Integrates Power Integrity Analysis and Fix into Design

Cadence Integrates Power Integrity Analysis and Fix into Design
by Bernard Murphy on 11-21-2023 at 6:00 am

Voltus Insight AI min

As integration levels increase, clock frequencies rise, and feature sizes shrink it is not surprising that all or most aspects of semiconductor design become more complex and demand more from design technologies. One example where the traditional approach is breaking down is in optimizing power distribution networks (PDNs)… Read More


Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Webinar: Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific
by Mike Gianfagna on 11-20-2023 at 2:00 pm

Webinar Silicon Catalyst & EE Times Examine the Bigger Picture Aspects of AI – Nov. 29, 2023 – 9am to 10am Pacific

Artificial Intelligence (AI) is dominating the news cycle these days. It used to be about the latest (and largest) chips to accelerate AI algorithms. While that’s still relevant and exciting, AI news is taking a much broader, socioeconomic character. What does AI mean for job security, the economy, or even life on Earth? These … Read More


Accelerating Development for Audio and Vision AI Pipelines

Accelerating Development for Audio and Vision AI Pipelines
by Bernard Murphy on 11-15-2023 at 6:00 am

AI pipeline min

I wrote previously that the debate over which CPU rules the world (Arm versus RISC-V) somewhat misses the forest for the trees in modern systems. This is nowhere more obvious that in intelligent audio and vision: smart doorbells, speakers, voice activated remotes, intelligent earbuds, automotive collision avoidance, self-parking,… Read More


Generative AI for Silicon Design – Article 3 (Simulate My Design)

Generative AI for Silicon Design – Article 3 (Simulate My Design)
by Anshul Jain on 11-14-2023 at 10:00 am

Generative AI for Silicon Design

Generative AI has time and again showcased its power to understand, predict, and explain a myriad of phenomena. Beyond its famed applications in art and text, it’s making ripples in the niche realm of hardware engineering. In this article, our exploration focuses on the potential of Generative AI to comprehend and predict… Read More


Podcast EP192: The Impact of SigmaSense on AI and Beyond with David French

Podcast EP192: The Impact of SigmaSense on AI and Beyond with David French
by Daniel Nenni on 11-08-2023 at 10:00 am

Dan is joined by David French, CEO of SigmaSense. David is best known for his 20-year focus on digital signal processors at Texas Instruments, and Analog Devices. In addition, he spearheaded the transition of Cirrus Logic’s business as its CEO, from a supplier of logic chips into personal computers to become a profitable… Read More


A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI

A Fast Path to Better ARC PPA through Fusion Quickstart Implementation Kits and DSO.AI
by Bernard Murphy on 11-07-2023 at 6:00 am

QIK+DSO.AI flow

Synopsys recently presented a webinar on using their own software to optimize one of their own IPs (an ARC HS68 processor) for both performance and power through what looks like a straightforward flow from initial configuration through first level optimization to more comprehensive AI-driven PPA optimization. Also of note … Read More


Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems… Read More