Improvements in SRAM Yield Variation Analysis

Improvements in SRAM Yield Variation Analysis
by Tom Dillinger on 03-27-2016 at 12:00 pm

The design of an SRAM array requires focus on the key characteristics of readability, writeability, and read stability. As technology scaling has enabled the integration of large (cache) arrays on die, the sheer number of bitcells has necessitated a verification methodology that focuses on “statistical high-sigma” variation… Read More


Key Takeaways from the TSMC Technology Symposium Part 2

Key Takeaways from the TSMC Technology Symposium Part 2
by Tom Dillinger on 03-22-2016 at 4:00 pm

In Part 1, we reviewed four of the highlights of the recent TSMC Technology Symposium in San Jose. This article details the “Final Four” key takeaways from the TSMC presentations, and includes a few comments about the advanced technology research that TSMC is conducting.… Read More


Analog Mixed-Signal Layout in a FinFET World

Analog Mixed-Signal Layout in a FinFET World
by Tom Dillinger on 03-20-2016 at 12:00 pm

The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More


DDR4 is a complex interface to verify — assistance needed!

DDR4 is a complex interface to verify — assistance needed!
by Tom Dillinger on 02-16-2016 at 7:00 am

The design of parallel interfaces is supposed to be (comparatively) easy — e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to the PCB trace impedance;… Read More


Top Ten Insights on the EDA and Semiconductor Industry

Top Ten Insights on the EDA and Semiconductor Industry
by Tom Dillinger on 02-11-2016 at 7:00 am

I recently had the opportunity to chat with Anirudh Devgan, senior vice president and general manager at Cadence, who leads the Digital and Signoff Group. We discussed recent product development initiatives at Cadence, and talked about future EDA and semiconductor market opportunities. His insights and comments were keen … Read More


Pathfinding to an Optimal Chip/Package/Board Implementation

Pathfinding to an Optimal Chip/Package/Board Implementation
by Tom Dillinger on 02-04-2016 at 4:00 pm

A new term has entered the vernacular of electronic design engineering — pathfinding. The complexity of the functionality to be integrated and the myriad of chip, package, and board technologies available make the implementation decision a daunting task. Pathfinding refers to the method by which the design space of technology… Read More


Expanding 3D EM Simulation Access to All

Expanding 3D EM Simulation Access to All
by Tom Dillinger on 02-03-2016 at 7:00 am

James Clerk Maxwell’s eponymous equations are the basis for simulating electromagnetic wave propagation. In school, EE majors tended to fall into two camps: (a) those that thoroughly enjoyed their fields and waves classes, who liked doing surface integrals, and who were adept at demonstrating the “right hand rule”, and (b) … Read More