I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”. The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications. In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing… Read More
Author: Mike Gianfagna
Filling the ASIC Void – Part 1
It started slowly at first. Then it began picking up steam. I’m referring to consolidation in the semiconductor sector. I had a front-row seat for what consolidation did to the ASIC part of semiconductor and that is the topic of this discussion. I was the VP of marketing at eSilicon, the company that invented the fabless ASIC model.… Read More
Security in I/O Interconnects
I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.
First, a bit about Richard. He is the technical… Read More
Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion
I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration… Read More
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More
Machine Learning for EDA – Inside, Outside and Everywhere Else
Artificial intelligence (AI) is everywhere. The rise of the machines is upon us in case you haven’t noticed. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making breakfast. We hear a lot about the macro, end-product impact of this technology, but there… Read More
5G SoCs Demand New Verification Approaches
Lately, I’ve been cataloging the number of impossible-to-verify technologies we face. All forms of machine learning and inference applications fall into this category. I’ve yet to see a regression test to prove a chip for an autonomous driving system will do the right thing in all cases. Training data bias is another interesting… Read More
Turbo-Charge Your Next PCIe SoC with PLDA Switch IP
SemiWiki has a new IP partner, PLDA and they bring a lot to the party. Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous… Read More
Achieving Design Robustness in Signoff for Advanced Node Digital Designs
I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More
Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips
At DesignCon 2020, there was a presentation by Micron, Socionext and Cadence that discussed design challenges and strategies for using the new low-power DDR specification (LPDDR5). As is the case with many presentations at DesignCon, ecosystem collaboration was emphasized. Justin Butterfield (senior engineer at Micron)… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot