De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue

De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue
by Mike Gianfagna on 02-12-2020 at 6:00 am

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At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations.  Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was… Read More


It’s The Small Stuff That Gets You …

It’s The Small Stuff That Gets You …
by Mike Gianfagna on 02-10-2020 at 6:00 am

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The last session I attended at DesignCon 2020 wasn’t a session at all. Rather it was an interactive discussion with Todd Westerhoff, product manager for electronic board systems at Mentor Graphics. Todd made some observations about the way high-performance PCBs are designed today and perhaps the way they should be designed. … Read More


AI Interposer Power Modeling and HBM Power Noise Prediction Studies

AI Interposer Power Modeling and HBM Power Noise Prediction Studies
by Mike Gianfagna on 02-07-2020 at 6:00 am

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I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling… Read More


Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
by Mike Gianfagna on 02-04-2020 at 10:00 am

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This year is the 25th anniversary for DesignCon.  The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.

The DesignCon technical program… Read More


Advanced ASICs – It Takes an Ecosystem

Advanced ASICs – It Takes an Ecosystem
by Mike Gianfagna on 11-26-2017 at 2:00 pm

I remember the days of the IDM (integrated device manufacturer). For me, it was RCA, where I worked for 15 years as the company changed from RCA to GE and then ultimately to Harris Semiconductor. It’s a bit of a cliché, but life was simpler then, from a customer point of view at least. RCA did it all. We designed all the IP, did the physical… Read More


The Future of Chip Design in the Internet Age

The Future of Chip Design in the Internet Age
by Mike Gianfagna on 05-20-2015 at 1:00 am

Huge designs, spectacular design costs, astronomical capital expenditure. Welcome to the present day semiconductor industry. As discussed in my prior post, the days of democratized silicon access have been replaced by an elite market. Custom chips are once again a rich person’s game. Does it have to stay this way? I personally… Read More


Chip Design – Coming of Age in the Computer Age

Chip Design – Coming of Age in the Computer Age
by Mike Gianfagna on 05-13-2015 at 2:30 am

Previously, I examined chip design in the late 1970s and early 1980s. It was a nostalgic ride – thanks to all those who shared their stories. I enjoyed reading all of them. I drew two basic conclusions in the prior post:

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  • Chip design problems are the same, more or less, over time. The numbers just get bigger
  • Raising abstraction
  • Read More

    Chip Design Problems Remain the Same, More or Less

    Chip Design Problems Remain the Same, More or Less
    by Mike Gianfagna on 05-09-2015 at 2:00 pm

    For those who may not know me, here is a brief introduction. I started in the semiconductor business when RCA was still making vacuum tubes and I wrote EDA software before there was an EDA industry. I’ve designed and sold chips and developed, sold and used EDA tools at companies as big as General Electric and as small as seven people.… Read More