Automotive-grade MIPI PHY IP drives multi-sensor solutions

Automotive-grade MIPI PHY IP drives multi-sensor solutions
by Don Dingee on 11-09-2023 at 10:00 am

Mixel Automotive PHY Solutions

Sensors are critical to every new automotive design, whether created for a driver or self-driving. Frame rates and resolution for car, truck, and SUV imaging systems continue to rise. Getting data from each sensor to a location in the vehicle with sufficient processing power may be challenging, especially when AI inference algorithms… Read More


Pairing RISC-V cores with NoCs ties SoC protocols together

Pairing RISC-V cores with NoCs ties SoC protocols together
by Don Dingee on 10-05-2023 at 6:00 am

An architecture pairing RISC-V cores with NoCs

Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting… Read More


Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows

Keysight EDA 2024 Delivers Shift Left for Chiplet and PDK Workflows
by Don Dingee on 09-28-2023 at 8:00 am

Chiplet PHY Designer

Much of the recent Keysight EDA 2024 announcement focuses on high-speed digital (HSD) and RF EDA features for Advanced Design System (ADS) and SystemVue users, including RF System Explorer, DPD Explorer (for digital pre-distortion), and design elements for 5G NTN, DVB-S2X, and satcom phased array applications. Two important… Read More


Deeper RISC-V pipeline plows through vector-scalar loops

Deeper RISC-V pipeline plows through vector-scalar loops
by Don Dingee on 09-14-2023 at 10:00 am

Atrevido 423 + V16 Vector Unit with its deeper RISC-V pipeline technology, Gazillion

Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled. A while back, Semidynamics… Read More


Scaling LLMs with FPGA acceleration for generative AI

Scaling LLMs with FPGA acceleration for generative AI
by Don Dingee on 09-13-2023 at 6:00 am

Crucial to FPGA acceleration of generative AI is the 2D NoC in the Achronix Speedster 7t

Large language model (LLM) processing dominates many AI discussions today. The broad, rapid adoption of any application often brings an urgent need for scalability. GPU devotees are discovering that where one GPU may execute an LLM well, interconnecting many GPUs often doesn’t scale as hoped since latency starts piling up with… Read More


Extending RISC-V for accelerating FIR and median filters

Extending RISC-V for accelerating FIR and median filters
by Don Dingee on 09-05-2023 at 10:00 am

Custom hardware blocks for FIR and median filters

RISC-V presents a unique opportunity for designers to extend the microarchitecture with custom instructions. One possible application is digital signal filtering using finite impulse response (FIR) or median filters, potential algorithms for carrier demodulation schemes in communications systems like 5G. Codasip application… Read More


Systematic RISC-V architecture analysis and optimization

Systematic RISC-V architecture analysis and optimization
by Don Dingee on 08-28-2023 at 10:00 am

RISC V architecture analysis and optimization chain

The RISC-V movement has taken off so quickly because of the wide range of choices it offers designers. However, massive flexibility creates its own challenges. One is how to analyze, optimize, and verify an unproven RISC-V core design with potential microarchitecture changes allowed within the bounds of the specification. … Read More


Points teams should consider about securing embedded systems

Points teams should consider about securing embedded systems
by Don Dingee on 07-18-2023 at 10:00 am

Connected devices in a home

Wishful thinking once prevailed that embedded systems, especially small embedded devices, rarely needed security, and if they did, simply installing a “secure” operating system or a security chip would keep them safe. Connecting devices big and small on the Internet of Things (IoT) shattered such insular thinking… Read More


400 GbE SmartNIC IP sets up FPGA-based traffic management

400 GbE SmartNIC IP sets up FPGA-based traffic management
by Don Dingee on 07-13-2023 at 10:00 am

Achronix ANIC

Sustaining wire-speed 400 GbE transfers is only a first step in managing enterprise traffic. Adding rules-based filtering to sift packets in real time can stress most networking hardware to a breaking point, slowing down an entire network. Architects are trying to spread these loads, distributing intelligent traffic management… Read More


Transforming RF design with curated EDA experiences

Transforming RF design with curated EDA experiences
by Don Dingee on 07-12-2023 at 10:00 am

How to Design an RF Power Amplifier course screenshot

Access to sophisticated RF EDA tools is one thing. Effectively harnessing their capability in real-world use is another. Digital EDA and test & measurement providers have long recognized ongoing customer education needs for their solutions. Keysight is embarking on an initiative to develop curated EDA experiences with… Read More