In my initial look at ClioSoft’s design management system created from the ground up for the semiconductor industry, I made the opening case for managing and reusing IP across an ASIC design organization. Let’s for a moment say we agree on the need for an enterprise software package to do design management… Read More
Author: Don Dingee
Enterprise Design Management Engineered for SoCs
Cross-viewing improves ASIC & FPGA debug efficiency
We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier… Read More
Get ready for hypergrade in automotive
With use cases expanding, the meaning of “automotive qualified” semiconductors is changing. What we’re now hearing about now is beyond the AEC-Q100 Grade 0 upper end of 150°C, while still meeting other reliability, retention, and security requirements. What does hypergrade mean for complex digital chip… Read More
Debugging is the whole point of prototyping
The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem.… Read More
Self-contained low power Wi-Fi IP for IoT apps
The emerging theme of fit-for-purpose IoT parts gained yet another perspective, this time with ARM and CEVA chiming in on a low-power Wi-Fi approach outlined in a new webinar. It was a rather unique event with an abbreviated 25-minute presentation and an extended 35-minute Q&A that added a lot of insight.… Read More
2.5D supply chain takes HBM over the wall
SoC designers have hit the memory wall head on. Although most SoCs address a relatively small memory capacity compared with PC and server chips, memory power consumption and bandwidth are struggling to keep up with processing and content expectations. A recent webinar looks at HBM as a possible solution.… Read More
Webinar alert – Taking UVM to the FPGA bank
UVM has become a preferred environment for functional verification. Fundamentally, it is a host based software simulation. Is there a way to capture the benefits of UVM with hardware acceleration on an FPGA-based prototyping system? In an upcoming webinar, Doulos CTO John Aynsley answers this with a resounding yes.… Read More
Webinar alert – Smart homes demanding low power Wi-Fi
There are two camps of thinking on the IoT: those who believe Bluetooth and Wi-Fi rule the edge, and those who support any of dozens of other wireless networking specifications for their various technical advantages. The ubiquity of Wi-Fi in homes helps devices connect in a few clicks – so why don’t more IoT designers use it?… Read More
Fit-for-purpose IoT ASICs are about more than cost
We’ve been saying for a while that it looks like there is a resurgence in design starts for ASICs targeting the IoT. A recent webinar featuring speakers from ARM and Open Silicon (and moderated by Daniel Nenni) affirms this trend, and provides some insight on how these designs may differ from typical microcontrollers.
One of my first… Read More
Optimizing memory scheduling at integration-level
In our previous post on SoC memory resource planning, we shared 4 goals for a solution: optimize utilization and QoS, balance traffic across consumers and channels, eliminate performance loss from ordering dependencies, and analyze and understand tradeoffs. Let’s look at details on how Sonics is achieving this.… Read More
Weebit Nano Moves into the Mainstream with Customer Adoption