An EDA Acquisition that Worked

An EDA Acquisition that Worked
by Daniel Payne on 08-14-2013 at 5:30 pm

I first heard about Andrew Yang back in 1993 when he founded a Fast SPICE company called Anagram, then acquired by Avant! in 1996. Andrew’s latest EDA company Apache Design, Inc.was started in 2001, then acquired by ANSYS in 2011. Most EDA mergers simply don’t work because of one or more reasons, like:

  • Incompatible
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RTL Design For Power

RTL Design For Power
by Daniel Payne on 08-11-2013 at 2:25 pm

My Samsung Galaxy Note II lasts about two days on a single battery charge, which is quite the improvement from the Galaxy Note I with only a one day battery charge. Mobile SoCs are being constrained by battery life limitations, and consumers love longer-laster devices.

There are at least two approaches to Design For Power:

  • Gate-level
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A Brief History of Docea Power

A Brief History of Docea Power
by Daniel Payne on 08-02-2013 at 2:55 pm



Founders

The founder, Ghislain Kaiser, spent about 10 years at STMicroelectronics, mainly in multimedia groups and for the wireless market. At this time, he was a power expert and tasked with making the chips use less power. The first thing he did was to look at what tools existed on the market. They wanted to use off the shelf tools… Read More


What Applications Implement Best with High Level Synthesis?

What Applications Implement Best with High Level Synthesis?
by Daniel Payne on 07-26-2013 at 3:12 pm

RTL coding using languages like Verilog and VHDL have been around since the 1980’s and for almost as long a time we’ve been hearing about High Level Synthesis, or HLS that allows an SoC designer to code above the RTL level where you code at the algorithm level. The most popular HLS languages today are C, C++ and SystemC.… Read More


Mixed Signal SOC verification Webinar

Mixed Signal SOC verification Webinar
by Daniel Payne on 07-16-2013 at 8:29 pm

When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

A second trend is the amount of Analog content in… Read More


Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs

Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs
by Daniel Payne on 07-15-2013 at 1:37 pm

On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More


Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube

Best Practices for Using DRC, LVS and Parasitic Extraction – on YouTube
by Daniel Payne on 07-10-2013 at 1:21 pm

EDA companies produce a wealth of content to help IC engineers get the best out of their tools through several means:

  • Reference Manuals
  • User Guides
  • Tutorials
  • Workshops
  • Seminars
  • Training Classes
  • Phone Support
  • AE visits
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Full Chip IR Drop Analysis using Distributed Multi Processing

Full Chip IR Drop Analysis using Distributed Multi Processing
by Daniel Payne on 07-02-2013 at 6:56 pm

IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared… Read More