HW Prototyping and HLS at DAC

HW Prototyping and HLS at DAC
by Daniel Payne on 06-28-2013 at 12:20 pm

I love it when EDA companies send their engineers to DAC because I learn more of the unvarnished truth about their products. I met with Bill Thomas of Aldec to get an update on their HW prototyping boards, then two NEC engineers to learn about High Level Synthesis.

HW Prototyping

Bill Thomas, Research Engineer at Aldec
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Validating Hard IP & Std Cell Libraries at DAC

Validating Hard IP & Std Cell Libraries at DAC
by Daniel Payne on 06-27-2013 at 3:13 pm

The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peetersof Fractal Technologiesat DAC.


Johan Peeters, Rene Donkers
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A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis

A 3D Field Solver for Parasitic Extraction Thermal ESD Analysis
by Daniel Payne on 06-27-2013 at 2:38 pm

The smaller the process node the more necessary it is that you extract accurate parasitics from interconnect and 3D structures in order to analyze timing, thermal effects and ESD compliance. Silicon Frontlinehas EDA tools in all three of these categories, so I met with Dermott Lynchat DAC to get an annual update.


Dermott Lynch,Read More


Visual AMS Debug, an update at DAC

Visual AMS Debug, an update at DAC
by Daniel Payne on 06-24-2013 at 4:07 pm

If you’re involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.


Gerhard Angst (center), Concept EngineeringRead More