Author: Daniel Payne

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Impact Conference: Focus on the IP Ecosystem

Impact Conference: Focus on the IP Ecosystem
by Daniel Payne on 12-11-2013 at 7:07 pm
Categories: EDA, Perforce

Jim Feldhan, President of Semico Research presented earlier this month at the Impact Conference on the topic: Focus on the IP Ecosystem. I’ve reviewed his 19 page presentation, and summarize it with:

  • End markets like smart phones and tablets are dominant
  • Growth drivers include the Internet of Things (IoT)
  • World semi forecast
… Read More
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Designing a DDR3 System to Meet Timing

Designing a DDR3 System to Meet Timing
by Daniel Payne on 12-11-2013 at 12:00 pm
Categories: EDA, Synopsys

My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More

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Capturing Analog Design Intent with Verification

Capturing Analog Design Intent with Verification
by Daniel Payne on 12-08-2013 at 10:05 am
Categories: EDA, Siemens EDA

Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More

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Virtual Prototypes Made Easier for SoC Design

Virtual Prototypes Made Easier for SoC Design
by Daniel Payne on 12-06-2013 at 6:24 pm
Categories: EDA

Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where… Read More

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Simplified Assertion Adoption with SystemVerilog 2012

Simplified Assertion Adoption with SystemVerilog 2012
by Daniel Payne on 12-02-2013 at 7:01 pm
Categories: Aldec, EDA

SystemVerilog as an assertion language improved and simplified with the 2012 version compared to the 2005 version. I recently viewed a webinar on SystemVerilog 2012 by consultant Srinivasan Venkataramanan, who works at CVC Pvt. Ltd. There’s been a steep learning-curve for assertions in the past, and hopefully you’ll… Read More

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Social Media at ARM

Social Media at ARM
by Daniel Payne on 11-26-2013 at 3:27 pm
Categories: Arm, IP

The number one semiconductor IP company in the world is ARM, and they have really figured out how to use social media in a big way to communicate with and listen to their customers. When you first visit the Home page for ARM there are four social media icons displayed in monochrome underneath the menu bar. As you hover over the icons (Twitter,… Read More

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Thermal Analysis for 3D SoC Integration

Thermal Analysis for 3D SoC Integration
by Daniel Payne on 11-21-2013 at 7:01 pm
Categories: EDA

The first time that I saw a DRAM in a ceramic package running on a tester I made the mistake of touching my finger to the metal lid, scorching my finger and teaching me a lesson that ICs can run extremely hot. I’ve read a lot the past few years about 3D IC design, and immediately my mind becomes curious about how an engineer would go… Read More

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Social Media at Synopsys

Social Media at Synopsys
by Daniel Payne on 11-15-2013 at 4:35 pm
Categories: EDA, Synopsys

When I talk about social media and mention Synopsys you may quickly think of Karen Bartleson, the Senior Director of Community Marketing, because she:

… Read More
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Bringing EDA to India

Bringing EDA to India
by Daniel Payne on 11-13-2013 at 1:00 pm
Categories: EDA, Events, Siemens EDA

Why do all three big EDA companies have user group meetings in India? The answer is to grow the EDA market in India because so many multi-national companies have engineers in India doing SoC, and IP design work. In my 35 years of IC design and EDA experience I’ve had the pleasure of working with and knowing many engineers and managers… Read More