A Hybrid Test Approach – Combining ATPG and BIST

A Hybrid Test Approach – Combining ATPG and BIST
by Daniel Payne on 09-09-2013 at 5:18 pm

In the world of IC testability we tend to look at various approaches as independent means to an end, namely high test coverage with the minimum amount of test time, minimum area impact, minimum timing impact, and acceptable power use. Automatic Test Pattern Generation (ATPG) is a software-based approach that can be applied to any… Read More


Test Compression and Hierarchy at ITC

Test Compression and Hierarchy at ITC
by Daniel Payne on 09-09-2013 at 8:00 am

The International Test Conference (ITC) is this week in Anaheim and I’ve just learned what’s new at Synopsys with test compression and hierarchy. Last week I spoke with Robert Ruiz and Sandeep Kaushik of Synopsys by phone to get the latest scoop. There are two big product announcements today that cover:… Read More


Low-Power Design Webinar – What I Learned

Low-Power Design Webinar – What I Learned
by Daniel Payne on 09-02-2013 at 7:00 pm

You can only design and optimize for low-power SoC designs if you can actually simulate the entire Chip, Package and System together. The engineers at ANSYS-Apachehave figured out how to do that and talked about their design for power methodology in a webinar today. I listened to Arvind Shanmugavel present a few dozen slides and… Read More


Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications

Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications
by Daniel Payne on 08-23-2013 at 7:36 pm

For several decades now consumers like me have enjoyed using mobile devices including:

  • Transistor radios, my first one had just 6 discreet transistors in the 1960’s
  • HP 21 Calculator, used in college with Reverse Polish Notation, circa 1976
  • Zenith Data Systems laptop, with two floppy drives, 1980’s
  • Palm Pilot V,
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Web-based Circuit Design and Analysis

Web-based Circuit Design and Analysis
by Daniel Payne on 08-21-2013 at 11:27 am

Last month I blogged about CircuitLaband received some two dozen comments, so clearly there is keen interest in using web-based tools for electronic circuit design and using the cloud to save designs plus run simulations. Today I’m reporting on TINACloud, provided by a company called DesignSoft. … Read More


Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More


Accelerating SoC Simulation Times

Accelerating SoC Simulation Times
by Daniel Payne on 08-15-2013 at 2:43 pm

There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More


An EDA Acquisition that Worked

An EDA Acquisition that Worked
by Daniel Payne on 08-14-2013 at 5:30 pm

I first heard about Andrew Yang back in 1993 when he founded a Fast SPICE company called Anagram, then acquired by Avant! in 1996. Andrew’s latest EDA company Apache Design, Inc.was started in 2001, then acquired by ANSYS in 2011. Most EDA mergers simply don’t work because of one or more reasons, like:

  • Incompatible
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RTL Design For Power

RTL Design For Power
by Daniel Payne on 08-11-2013 at 2:25 pm

My Samsung Galaxy Note II lasts about two days on a single battery charge, which is quite the improvement from the Galaxy Note I with only a one day battery charge. Mobile SoCs are being constrained by battery life limitations, and consumers love longer-laster devices.

There are at least two approaches to Design For Power:

  • Gate-level
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A Brief History of Docea Power

A Brief History of Docea Power
by Daniel Payne on 08-02-2013 at 2:55 pm



Founders

The founder, Ghislain Kaiser, spent about 10 years at STMicroelectronics, mainly in multimedia groups and for the wireless market. At this time, he was a power expert and tasked with making the chips use less power. The first thing he did was to look at what tools existed on the market. They wanted to use off the shelf tools… Read More