Video webinars are a main staple to learn what’s new about EDA tools and methodologies, but there’s nothing quite like meeting in person, where you can ask questions and gauge the expertise of the presenters. I was delighted to learn that Keysight is planning a literal world tour to update EDA customers and prospects on what they … Read More
Author: Daniel Payne
Keysight EDA Connect World Tour
Making UVM faster through a new configuration system
The Universal Verification Methodology (UVM) is a popular way to help verify SystemVerilog designs, and it includes a configuration system that unfortunately has some speed and usage issues. Rich Edelman from Siemens EDA wrote a detailed 20-page paper on the topic of how to avoid these issues, and I’ve gone through it to… Read More
Using PCB Automation for an AI and Machine Vision Product
I knew that HDMI was a popular standard used to connect consumer products like a monitor to a laptop, but most professional video and broadcast systems use the SDI (Serial Digital Interface) connector standard. Pleora Technologies, founded in 2000, currently serves the machine vision and manufacturing markets, including those… Read More
SystemVerilog Has Some Changes Coming Up
SystemVerilog came to life in 2005 as a superset of Verilog-2005. The last IEEE technical committee revision of the SystemVerilog LRM was completed in 2016 and published as IEEE 1800-2017.
Have the last seven years revealed any changes or enhancements that maintain SystemVerilog’s relevance and efficaciousness in the face … Read More
Handling metastability during Clock Domain Crossing (CDC)
SoC designs frequently have lots of different clock domains to help manage power more efficiently, however one side effect is that when the clock domains meet, i.e., in a Clock Domain Crossing (CDC), there’s the possibility of setup and hold time violations that can cause a flip-flop to become metastable. Synchronizer … Read More
New STA Features from Cadence
Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when… Read More
Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More
SRAM design analysis and optimization
Every year EDA vendor MunEDA hosts a user group meeting where engineers present how they used automation tools to improve their IC designs, and one presentation from Peter Huber of Infineon caught my attention, it was all about SRAM design optimization. Peter has authored papers at IEEE conferences and been issued patents related… Read More
Managing IP, Chiplets, and Design Data
Design re-use has enabled IC design teams to create billion-transistor designs where hundreds of IP blocks are pre-built from internal or external sources. Keeping track of where each of these IP blocks came from, what their version status is, managing IP, or even discerning their license status can be a full-time job if tracked… Read More
An Update on IP-XACT standard 2022
Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges. Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI