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SystemVerilog Has Some Changes Coming Up

SystemVerilog Has Some Changes Coming Up
by Daniel Payne on 11-29-2023 at 10:00 am

SystemVerilog came to life in 2005 as a superset of Verilog-2005. The last IEEE technical committee revision of the SystemVerilog LRM was completed in 2016 and published as IEEE 1800-2017.

Have the last seven years revealed any changes or enhancements that maintain SystemVerilog’s relevance and efficaciousness in the face of rapidly evolving technology? Why yes! Engineers are continually wanting more features, improved clarity of the specification, and fixes to the previous versions.

Starting in 2019, the technical committee started work on the proposed standard P1800-2023, with a plan of final publication in 2024. The 1800-2023 standard benefits from hundreds of corrections, clarifications, and enhancements to the LRM to keep the language current. Dave Rich from Siemens EDA wrote a nine-page paper going into the details of some of these changes. In this article, I’ll highlight just a few of the enhancements discussed in his paper.

Enhancements

Coverpoints are being extended so that covergroups have inheritance. The new syntax will allow you to write a class with covergroups like this:

class pixel; // original base class
 bit [7:0] level;
 enum {OFF,ON,BLINK,REVERSE} mode;
 covergroup g1;
   a: coverpoint level;
   b: coverpoint mode;
 endgroup
 function new(); 
   g1 = new;
 endfunction
endclass

class colorpixel extends pixel; // extended covergroup in extended class
 enum {red,blue,green} color;
 covergroup extends g1;
  b: coverpoint mode { // override the 
  coverpoint ‘b’ from the base class 
   ignore_bins ignore = {REVERSE}; 
  }
  cross a color; // ‘a’ comes from the base class 
 endgroup 
endclass

Arrays will now allow you to cast their elements to a new type, and operate on each element, like in these examples:

int A[3] = {1,2,3}; 
byte B[3]; 
int C[3]; // assigns and casts array of int to an array of byte 
B = A.map() with ( byte’(item) ); 
// increments each element of the  array (use b instead of item) 
B = B.map(b) with ( b + 8’b1 ); 
// B becomes {2,3,4} 
// Add two arrays 
C = A.map(a) with (a + B[a.index] ); 
// C becomes {3,4,5}

The ifdef statement will support Boolean expressions in parenthesis, reducing the number of lines required, like this:

`ifdef (A && B)
 // code for AND condition 
`endif 
`ifdef (A || B) 
// code for OR condition 
`endif

Multi-line strings are supported using a triple quote syntax:

string x = “”” 
This is one continuous string. 
Single ‘ and double “ can be placed 
throughout, and only a triple quote will end it. 
“””

Real number modeling has been added to better model AMS designs. The syntax using real numbers with covergroup looks like:

coverpoint r {
 type_option.real_interval= 0.02;
 bins b[] = {[0.75:0.85]};
 // 10 bins
 // b[0] 0.75 to less than 0.76
 // b[1] 0.76 to less than 0.77
 // . . .
 // b[9] 0.84 to less than or equal to 0.85 
}

With the chaining of method calls you can use a function result as a variable for choosing a member of the result.  Here’s an example:

class A;
 int member=123;
endclass 
module top; 
 A a; 
 function A F(int arg=0); 
  int member; // static variable 
  uninitialized value 0
  a = new();
  return a; 
 endfunction
 initial begin 
  $display(F.member); // 0 – No 
  “()”, Verilog hierarchical reference 
  $display(F().member); // 123 – With 
  “()”, implicit variable 
 end 
endmodule

There’s now support for adding a static qualifier to a formal ref argument, assuring that the actual argument has a static lifetime.

module top;
 function void monitor(ref static 
 logic arg);
  fork // the reference to arg only 
  becomes legal with a static 
  qualifier 
   forever @(arg) $display(“arg 
   changed at time %t”, arg, 
   $realtime); 
  join_none 
 endfunction 
 logic C; 
 initial monitor(C); 
endmodule

Summary

SystemVerilog users will reap the benefits of staying current with the proposed changes coming for the language. If your favorite features weren’t proposed for this release, then why not get involved with the technical committee to have your voice heard and make SystemVerilog even better for the next version.

Read the complete Nine-page paper from Dave Rich at Siemens EDA.

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