MEMS Update from DAC

MEMS Update from DAC
by Daniel Payne on 06-11-2014 at 11:32 am

DAC has an interesting mix of vendors each year, and some of them are outside of the expected digital, analog or IP space. Last Tuesday at DAC I visited a company called Coventor that has three product lines:

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An Update on Calibre at DAC

An Update on Calibre at DAC
by Daniel Payne on 06-09-2014 at 12:00 pm

Even though I live just 7 miles away from the Mentor Graphics corporate office in Oregon, I visited their DAC suite in San Francisco last week to get an update on Calibrefrom Michael White. The Calibre tools are used during IC verification and sign-off by performing DRC (Design Rule Checking) and LVS (Layout Versus Schematic).… Read More


IoT Breakfast Panel at DAC

IoT Breakfast Panel at DAC
by Daniel Payne on 06-03-2014 at 7:21 pm

Tuesday morning at DAC I enjoyed a free breakfast courtesy of Synopsysand GLOBALFOUNDRIESwhere I learned more about the emerging market of IoT, and what it means to semiconductor, EDA and IP vendors. Panelists included: Semico Research, HP, Synopsys, GLOBALFOUNDRIES and Broadcom. … Read More


High Sigma Yield Analysis and Optimization at DAC

High Sigma Yield Analysis and Optimization at DAC
by Daniel Payne on 06-02-2014 at 7:20 pm

When I hear the phrase “high sigma” I think of the EDA vendor Solido, however at DAC on Monday I visited another EDA company called MunEDAthat has several products of interest to transistor-level IC designers. I was able to speak with three different people from MunEDA and here’s what I learned.… Read More


Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS

Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS
by Daniel Payne on 05-31-2014 at 9:20 pm

My former co-worker, Kenneth Bakalar at Mentor Graphics is an expert in AMS modeling languages and UPFmethodology, so he recently teamed up with Eric Jeandeau to author an interesting white paper: Interpreting UPF for a Mixed-Signal Design Under Test. This white paper is based on a presentation made at DVCon earlier this year.… Read More


How About a Quality-Aware IP Design Flow

How About a Quality-Aware IP Design Flow
by Daniel Payne on 05-28-2014 at 6:18 pm

In the EDA world we use hyphens quite often to describe our technical approaches, like: DFM-aware, Power-aware, Variation-aware. I just read a white papertoday on the topic of Quality-Aware IP Design Flows, written by Fractal Technologies. If your group creates IP or re-uses IP, then there’s always the question about … Read More


Two New ESL Tools for Power and Thermal at DAC

Two New ESL Tools for Power and Thermal at DAC
by Daniel Payne on 05-27-2014 at 6:47 pm

Gary Smith published a list of what to see at DAC, and I noticed that he listed DOCEA Power in a category of ESL Thermal. I’ll be meeting the DOCEA engineers on Wednesday at DAC to learn more about their two newest ESL products:

  • Thermal Profiler
  • Power Intelligence

In general DOCEA Power tools allow you to manage power and thermal… Read More