Author: Daniel Payne

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A New Product for DRC and LVS that Lives in the Cloud

A New Product for DRC and LVS that Lives in the Cloud
by Daniel Payne on 04-17-2017 at 12:00 pm
Categories: Cadence, EDA

Back in the day the Dracula tool from Cadence was king of the DRC and LVS world for physical IC verification, however more recently we’ve seen Calibre from Mentor Graphics as the leader in this realm. Cadence wanted to reclaim their earlier prominence in physical verification so they had to come out with something different… Read More

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How to Implement a Secure IoT system on ARMv8-M

How to Implement a Secure IoT system on ARMv8-M
by Daniel Payne on 04-14-2017 at 12:00 pm
Categories: Arm, EDA, IoT, Security

This weekend my old garage door opener started to fail, so it was time to shop for a new one at The Home Depot, and much to my surprise I found that Chamberlain offered a Smartphone-controlled WiFi system. Just think of that, controlling my garage door with a Smartphone, but then again the question arose, “What happens when a … Read More

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Communication with Smart, Connected Devices and AI

Communication with Smart, Connected Devices and AI
by Daniel Payne on 04-12-2017 at 12:00 pm
Categories: AI, EDA, Events, General

I’ve lived and worked in Silicon Valley for 13 years, but since 1995 I’ve been in the Silicon Rainforest (aka Oregon) where the world’s number one semiconductor company Intel, has a large presence, along with dozens of smaller high-tech firms. In the past year I’ve started to attend events organized … Read More

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Lowering Costs for Custom SoC Development – ARM and Tanner EDA

Lowering Costs for Custom SoC Development – ARM and Tanner EDA
by Daniel Payne on 03-31-2017 at 12:00 pm
Categories: Arm, EDA, IoT, IP, Siemens EDA, Tanner EDA

Cost is a major barrier when an electronic design company starts to consider developing a custom SoC for a particular market segment. But what if there was a way to lower the development cost, or even get to an SoC proof of concept for no cost except of course for your engineering expenses? That value proposition caught my attention… Read More

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Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm
Categories: EDA, Events

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More

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Seven Reasons to Use FPGA Prototyping for ASIC Designs

Seven Reasons to Use FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-28-2017 at 12:00 pm
Categories: EDA, FPGA, Open-Silicon

Using an FPGA to prototype your next hardware design is a familiar concept, extending all the way back to the time that the first FPGAs were being produced by Xilinx and Altera. There are multiple competitors in the marketplace for FPGA prototyping, so I wanted to discern more about what the German-based company PRO DESIGN had to … Read More

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How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA

How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA
by Daniel Payne on 03-23-2017 at 12:00 pm
Categories: Arm, EDA, Siemens EDA, Tanner EDA

Leading edge SoC designs can contain billions of transistors, cost over $10M to design, and take over 18 months to deliver, but not all SoCs require that much complexity, cost and time. In fact, there is a growing class of SoC designs that integrate the popular ARM Cortex-M0 processor along with analog blocks that work with sensors… Read More

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Joe Costello and Other Luminaries Keynote at DAC

Joe Costello and Other Luminaries Keynote at DAC
by Daniel Payne on 03-20-2017 at 12:00 pm
Categories: EDA, Events, IoT

The most charismatic EDA CEO that I have ever witnessed is Joe Costello, who formed Cadence by merging SDA (Solomon Design Automation) and ECAD (known for DRC with Dracula). You will be impressed with his Monday keynote at DACon June 19th, starting at 9:15AM. Joe has long since left the EDA world and is currently the CEO of a company… Read More

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Six Reasons to Consider Using FPGA Prototyping for ASIC Designs

Six Reasons to Consider Using FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-15-2017 at 12:00 pm
Categories: EDA, Events, FPGA, Open-Silicon

There’s no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there’s always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers… Read More

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Securing Your IoT System using ARM

Securing Your IoT System using ARM
by Daniel Payne on 03-14-2017 at 12:00 pm
Categories: Arm, EDA, IoT, IP, Security

I’ll never forget reading about and experiencing the October 21, 2016 Distributed Denial of Service (DDoS) attacks which slowed and shut down a lot of the Internet. On that particular attack the target was to shut down the Domain Name System (DNS). Traffic for this massive DDoS attack came from IoT devices which were unsecured… Read More