Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Using AI in EDA for Multidisciplinary Design Analysis and Optimization
by Daniel Payne on 07-04-2022 at 10:00 am

Optimality min

Most IC and system engineers follow a familiar process when designing a new product: create a model, use parameters for the model, simulate the model, observe the results, compare results versus requirements, change the parameters or model and repeat until satisfied or it’s time to tape out. On the EDA side, most tools perform… Read More


Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart… Read More


Using STA with Aging Analysis for Robust IC Designs

Using STA with Aging Analysis for Robust IC Designs
by Daniel Payne on 06-23-2022 at 10:00 am

Gate Level Aging min

Our laptops and desktop computers have billions of transistors in their application processor chips, yet I often don’t consider the reliability effects of aging that the transistors experience in the chips. At the recent Synopsys User Group (aka SNUG), there was a technical presentation on this topic from Srinivas Bodapati,… Read More


Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am

XLR min

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott… Read More


Methods for Current Density and Point-to-point Resistance Calculations

Methods for Current Density and Point-to-point Resistance Calculations
by Daniel Payne on 05-26-2022 at 10:00 am

ESD path min

IC reliability is an issue that circuit design engineers and reliability engineers are concerned about, because physical effects like high Current Density (CD) in interconnect layers, or high point-to-point (P2P) resistance on device interconnect can impact reliability, timing or Electrostatic Discharge (ESD) robustness.… Read More


3D IC Update from User2User

3D IC Update from User2User
by Daniel Payne on 05-24-2022 at 10:00 am

FO WLP min

Our smart phones, tablets, laptops and desktops are the most common consumer products with advanced 2.5D and 3D IC packaging techniques. I love seeing the product tear down articles to learn how advanced packaging techniques are being used, so at the User2User conference in Santa Clara I attended a presentation from Tarek Ramadan,… Read More


Joseph Sawicki of Siemens EDA at User2User

Joseph Sawicki of Siemens EDA at User2User
by Daniel Payne on 05-19-2022 at 10:00 am

Joseph Sawicki

I attended the annual user group meeting called User2User in Santa Clara this year, hosted by Siemens EDA, with 51 presentations by customers in 11 tracks, and keynotes during each lunch hour from semiconductor executives. Joseph Sawicki, Executive VP, IC Segment, at Siemens EDA presented on a Tuesday, along with Prashant Varshney,… Read More


Cybersecurity Threat Detection and Mitigation

Cybersecurity Threat Detection and Mitigation
by Daniel Payne on 05-16-2022 at 10:00 am

Embedded Analytics min

Every week in the technology trade press I am reading about cybersecurity attacks against web sites, apps, IoT devices, vehicles and even ICs. At the recent IP SoC Silicon Valley 2022 event in April I watched a cybersecurity  presentation from Robert Rand, Solution Architect for Tessent Embedded Analytics at Siemens EDA. Common… Read More


High-speed, low-power, Hybrid ADC at IP-SoC

High-speed, low-power, Hybrid ADC at IP-SoC
by Daniel Payne on 05-10-2022 at 10:00 am

hybrid adc min

Andrew Levy and I both worked at Intel and Opmaxx, and I knew that he was now working at Alphacore, an IP company specializing in mixed-signal, RF, imaging and rad-hard applications. I was curious what Alphacore was up to, so at the IP-SoC Silicon Valley 2022 event I watched the ADC presentation from Ken Potts, COO of Alphacore. Mr.… Read More


Designing Ultra-Low-Power, Always On IP

Designing Ultra-Low-Power, Always On IP
by Daniel Payne on 05-09-2022 at 10:00 am

processor and sensor trends min

It’s popular to use DSP chips for vision processing in diverse applications like ADAS, security cameras and AR. Tensilica has been designing DSP chips and IP since 1997, and their technology was successful enough that Cadence acquired Tensilica back in 2013. At the IP-SoC Silicon Valley 2022 event in April I had the pleasure… Read More