16nm FinFET versus 20nm Planar!

16nm FinFET versus 20nm Planar!
by Daniel Nenni on 11-04-2012 at 8:10 pm

The common theme amongst semiconductor ecosystem conferences this year is FinFETS, probably the most exciting technology we will see this decade. A lot has been written on SemiWiki about FinFETS, it is one of the top trending search terms, but there is some confusion about the process naming so let me attempt to explain.

In planar… Read More


ARM TechCon 2012 Trip Report

ARM TechCon 2012 Trip Report
by Daniel Nenni on 11-02-2012 at 12:00 pm

I must say the ARM conference gets better every year, as do the attendance numbers. More than 4,000 people showed up including 5 SemiWiki bloggers, two of which I had not yet had the pleasure of meeting.

First I have to mention my favorite vendor booth. I don’t remember what company it was but the girls in fishnet stockings giving out… Read More


Apple v. Samsung: Mixed Phone Marriages End in Divorce?

Apple v. Samsung: Mixed Phone Marriages End in Divorce?
by Daniel Nenni on 10-28-2012 at 8:10 pm

A funny thing happened at dinner the other night. The SemiWiki blog “8 Things I Hate about My iPhone5” caused quite a discussion. Half the table had Samsung phones and the other half iPhones. It really was more of a religious or political debate versus a rational consumer electronic discussion. An interesting side note, it seems … Read More


A Brief History of Today’s Flexible ASIC Model

A Brief History of Today’s Flexible ASIC Model
by Daniel Nenni on 10-25-2012 at 8:10 pm

There’s been an interesting trend emerging the past couple of years; a gentrification, if you will, of the ASIC business. What was thought to be a dying supply chain model has re-emerged as a health and growing segment of the semiconductor industry. Recent figures from Gartner place 2012 ASIC revenue at around $24.4 billion… Read More


Why Blog on SemiWiki.com?

Why Blog on SemiWiki.com?
by Daniel Nenni on 10-21-2012 at 7:00 pm

The Semiconductor Wiki Project, the premier semiconductor collaboration site, is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem. Since going online January 1st, 2011 more than 400,000 unique visitors have landed at www.SemiWiki.com viewing more than 3M pages… Read More


TSMC OIP Forum 2012 Trip Report!

TSMC OIP Forum 2012 Trip Report!
by Daniel Nenni on 10-21-2012 at 6:00 pm

The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for … Read More


Current Timing Closure Techniques Can’t Scale – Requires New Solution

Current Timing Closure Techniques Can’t Scale – Requires New Solution
by Daniel Nenni on 10-16-2012 at 8:30 pm


There’s a nice article on timing closure by Dr. Jason Xing, Vice President of Engineering at ICScape Inc. on the Chip Design website. Not familiar with ICScape? Paul McLellan called ICScape the The Biggest EDA Company You’ve Never Heard Ofand Daniel Payne did Schematic, IC Layout, Clock and Timing Closure from ICScape atRead More


Oct. 18 Non-Volatile Memory Webinar, IBM validates OTP for Foundry program, & New Low-Risk Evaluation License

Oct. 18 Non-Volatile Memory Webinar, IBM validates OTP for Foundry program, & New Low-Risk Evaluation License
by Daniel Nenni on 10-16-2012 at 9:37 am

As the temperature drops and the bright red maple leaves have begun to pile up, so has the stack of projects at Novocell. If you are expecting to utilize their high reliability, easy-to-integrate OTP in a project taping out in late Q4 or early Q1, NOW is the time to contact them.

OTP Overview Webinar Thurs, Oct 18

Novocell and global … Read More


Power Integrity Challenges for High Speed and High Frequency Designs

Power Integrity Challenges for High Speed and High Frequency Designs
by Daniel Nenni on 10-14-2012 at 8:30 pm

There is an interesting discussion on the LinkedIn SoC Power Integrity Group in regards to the power integrity challenges for high speed and high frequency designs. More specifically, the additional attention an on-chip power delivery network (PDN) requires as the operating frequency of ICs and SoCs increases.

The PDN has to… Read More


Advanced Node Design Webinar Series

Advanced Node Design Webinar Series
by Daniel Nenni on 10-14-2012 at 8:15 pm


At advanced process nodes, variation and its effects on the design become a huge challenge. Join Cadence® Virtuoso® experts for a series of technical webinars on variation-aware design. Learn how to use advanced technologies and tools to analyze and understand the affects of variation. We’ll introduce you to the latest Virtuoso… Read More