The relentless miniaturization of semiconductor devices has always relied on achieving ever-smaller features on silicon wafers. However, as the industry enters the realm of extreme ultraviolet (EUV) lithography, it faces a critical barrier: stochastics, or the inherent randomness in patterning at atomic scales. This phenomenon… Read More
Author: Admin
Closing the Stochastics Resolution Gap
Godfather of AI: I Tried to Warn Them But We’ve Already Lost Control!
Geoffrey Hinton, dubbed the “Godfather of AI,” joins Steven Bartlett on “The Diary of a CEO” podcast to discuss his pioneering work in neural networks and his growing concerns about AI’s dangers. Hinton, a Nobel Prize-winning computer scientist, explains how he advocated for brain-inspired… Read More
Improve Precision of Parasitic Extraction for Digital Designs
By Mark Tawfik
Parasitic extraction is essential in integrated circuit (IC) design, as it identifies unintended resistances, capacitances, and inductances that can impact circuit performance. These parasitic elements arise from the layout and interconnects of the circuit and can affect signal integrity, power consumption,… Read More
Dual Strategy of Electroless Metal Deposition and Surface Silylation Toward Scalable Low-Temperature Hybrid Bonding for Advanced Packaging Applications
In extreme ultraviolet lithography (EUVL) systems, the collector mirror is a critical optical component that gathers and directs EUV light from the source toward the projection optics. Over time, the collector surface accumulates contaminant films — primarily tin (Sn) debris from the laser-produced plasma (LPP) source, … Read More
Rethink Scoreboards to Supercharge AI-Era CPUs
By Dr. Thang Minh Tran, CEO/CTO Simplex Micro
Today’s AI accelerators—whether built for massive data centers or low-power edge devices—face a common set of challenges: deep pipelines, complex data dependencies, and the high cost of speculative execution. These same concerns have long been familiar in high-frequency microprocessor… Read More
Jitter: The Overlooked PDN Quality Metric
Bruce Caryl is a Product Specialist with Siemens EDA
The most common way to evaluate a power distribution network is to look at its impedance over the effective frequency range. A lower impedance will produce less noise when transient current is demanded by the IC output buffers. However, this transient current needs to be provided… Read More
Silvaco’s Diffusion of Innovation: Ecosystem Investments Driving Semiconductor Advancements
In Silvaco’s June 2025 Tech Talk, “The Diffusion of Innovation: Investing in the Ecosystem Expansion,” Chief Revenue Officer Ian Chen outlined how strategic partnerships accelerate R&D in semiconductor design and digital twin modeling. As a leading provider of TCAD, EDA software, and SIP solutions,… Read More
Legacy IP Providers Struggle to Solve the NPU Dilemna
At Quadric we do a lot of first-time introductory visits with prospective new customers. As a rapidly expanding processor IP licensing company that is starting to get noticed (even winning IP Product of the Year!) such meetings are part of the territory. Which means we hear a lot of similar sounding questions from appropriately… Read More
Advancements in 3D Stacked IGZO 2T0C DRAM for Computing-in-Memory Applications
In the rapidly evolving field of artificial intelligence (AI), the demand for efficient data processing has exposed limitations in traditional memory technologies. The paper “3D Stacked IGZO 2T0C DRAM Array with Multibit Capability for Computing in Memory Applications,” published in Science Advances on May… Read More
Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination
Resistive RAM (ReRAM or RRAM) is the strongest candidate for next-generation non-volatile memory (NVM), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called ‘relaxation’ are making ReRAM more predictable — and easier to specify for real-world applications.… Read More
ASML High-NA EUV is Not Ready for High-Volume Production