WP_Term Object
    [term_id] => 77
    [name] => Sonics
    [slug] => sonics
    [term_group] => 0
    [term_taxonomy_id] => 77
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 49
    [filter] => raw
    [cat_ID] => 77
    [category_count] => 49
    [category_description] => 
    [cat_name] => Sonics
    [category_nicename] => sonics
    [category_parent] => 14433

Dark Silicon

Dark Silicon
by Paul McLellan on 05-26-2014 at 5:29 pm

 One of the problems with chips today is that of so-called “dark silicon”. We can put massive functionality on an SoC today. A billion transistors, and that is just at 28nm. But power constraints (both leakage and dynamic power) limit how much of the chip can be powered up at any one time. In some cases this is not that big an issue: if your cell-phone is not making a call then don’t power up the transmit/receive logic. But in other cases it is a huge problem. There is absolutely no point in putting a 16-core processor on a chip and then finding that 10 is the maximum number of cores that can be on at any one time. The cores are identical, so it is not like the transmit/receive logic case that I just mentioned.

At the Linley Microprocessor Conference a couple of weeks ago, Drew Wingard, the CTO of Sonics presented on this, although the presentation was actually called Power Management Advances for Heterogenous Mobile Systems although as a marketing guy I prefer to talk about the problem of dark silicon

They see it as an opportunity for further power optimization. One of the thing a network-on-chip (NoC) buys you is that the power management can be much more automated. The NoC “knows” if a block is powered down when a message arrives for it and can buffer the message, power up the block and then deliver it. This makes it possible to do much more aggressive power management without depending on the embedded software people, who barely understand how the chip works, to do it through flipping register bits.

There are also lots of chip-level techniques for reducing power. Reduce the clock frequency. Turn the clock off when nothing useful is being done on that part of the chip. Power down the block completely. But for all these to be done safely it all needs to be architected into the IP. There are huge savings but it is very hard to get at them , for example, with a standard bus-based fabric: the bus must be powered if any of the attached cores are on and then the internals of the block may be powered off or not be being clocked.

The alternative approach taken by Sonics is to use the network to enable power domains. The network itself can also be partitioned inside power domains. With intelligence in the network it is much easier to shut down power domains safely and automatically wake up components by holding traffic and then sending a request to the system power manager.

SonicsGN is a power-aware on-chip network that can cope with all this. For example in the above diagram the network handles the SoC for a tablet computer including domain partitioning, clock gating and domain on/off control. This enables much finer grained power control, is safer, requires less CPU overhead and all sorts of other benefits (not least that because it is in hardware the CPU might not even need to be on). Potentially these approaches can save half of the total SoC power consumption.

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