Networking through dark silicon power islands

Networking through dark silicon power islands
by Don Dingee on 12-27-2015 at 7:00 am

For decades, tracing back to the days of Deming, the way to tackle complex engineering problems has been the pareto chart. Charting conditions and their contribution to the problem leads to mitigation priorities.

In the case of SoC power management, the old school pareto chart said the processor core was the biggest power hog and… Read More


A Novel Microprocessor Fighting Dark Silicon, Energy Efficiency, Code density and Silicon area

A Novel Microprocessor Fighting Dark Silicon, Energy Efficiency, Code density and Silicon area
by Roger Sundman on 11-12-2015 at 4:00 pm

Processor cores used in computers and smartphones have become impaired by their own complexity and can’t fully utilize future CMOS generations for increasing their efficiency. Due to the continued increase of density and speed of transistors, these big cores produce too much heat per mm[SUP]2[/SUP] if trying to follow Moore’s… Read More


Dark Silicon

Dark Silicon
by Paul McLellan on 05-26-2014 at 5:29 pm

One of the problems with chips today is that of so-called “dark silicon”. We can put massive functionality on an SoC today. A billion transistors, and that is just at 28nm. But power constraints (both leakage and dynamic power) limit how much of the chip can be powered up at any one time. In some cases this is not that big… Read More