The push for autonomous automobiles continues at a rapid pace. Last week a new conference was held in Santa Clara, CA by the Linley Group focused on Autonomous Hardware. The group included presentations from GLOBAL FOUNDRIES, Synopsys, NetSpeed Systems, Arteris, EMBC, Cadence, CEVA, ARM and Trilumina covering ADAS and autonomous driving, deep learning, and processors for autonomous vehicles.
Being an ASIC guy for many years, I was intrigued by the sheer complexity of the ICs being presented to handle the tasks of autonomous driving. These ICs epitomize a true systems-on-a-chip. The thing that sets these ICs apart for me is the fact that they are not merely pipelining or combining more of the same logic onto a die. They are very heterogeneous in nature with many different IP cores being used, all of which have different interfaces, performance and latency characteristics. Added to this is that fact that many of these IPs must share common memory and interact with each other. This implies employment of a sophisticated memory coherency strategy across the overall system architecture. Lastly, these ICs are going to be used to drive your car! That means they must be fault tolerant and able to work continuously without errors or deadlocks.
As a physical design guy, I know that if the logic is regular and repeated that the layout tasks and timing closure will be more or less straight forward. While these ICs have logic within IP blocks that is regular and repeated, the interconnection between these IPs is another challenge altogether. Because of the complexity of the devices and different interfaces for each, many IC suppliers are now opting to use a Network-on-Chip (NoC) to handle their interconnect. So much for routing wide buses around the chip between the IPs (a nightmare if you’ve ever had to do it).
The question then is the whether the medicine is worse than the cure. Once you move to a NoC, it’s like you introduced an entirely new IC within an IC except this new design must be distributed around the full IC’s IP blocks to enable inter-IP connections that must be made. Think of it as a distributed IC within an IC. This means you have an entirely new architecture that must be designed that will literally manage the full IC. Enter NetSpeed Systems to the rescue!
Anush Mohandass of NetSpeed Systems gave a very good presentation on how they enable designers to design and implement these complex NoCs, including helping designers make the difficult trade-offs between power, performance, area and functional safety (FuSa). The logic that implements the NoC has many different tasks to perform. This includes data translation for each IP’s interface to a common NoC format, efficient routing of data packets between IPs, error checking for fault tolerance, load balancing and dynamic routing adjustments to comprehend changing data traffic patterns between. All of this must be done while meeting user-specified quality of service (QoS) targets and avoiding deadlock situations. Additionally there is a need to also include on-the-fly security checking to ensure the IC is not being compromised by some agent trying to take over control from the outside. The main attack surface for these types of ICs is the NoC, as the NoC controls all data going into and out of the rest of the system.
NetSpeed offers a design and optimization cockpit called NocStudio that employs a top-down approach using machine learning to optimize the IC’s NoC-based QoS, power, performance, area, latency and FuSa. NocStudio analyzes different approaches to the power, performance, area and FuSa trade-offs and then synthesizes a NoC that best meets the designers’ goals. Designers can weight and customize the trade-offs depending on the end application and markets that their SoC serves. This includes the ability to categorize data packet traffic in up to 16 different classes and allocate up to 64 virtual channels with dynamic priority to allow for dynamic QoS control.
Functional Safety is considered a first-class citizen of the SoC from the very beginning, rather than as something that is tacked on at the end. NetSpeed’s NoC IP is certified ISO 26262 ASIL Level-D ready but the software also gives designers the flexibility to divide the NoC into different ASIL-level partitions depending on the needs of their clients. NetSpeed’s machine learning algorithms can synthesize the different partitions to different ASIL levels per the designers’ request as it also knows how to grade the circuit per the ISO 26262 standard. It does all of this while also ensuring that the NoC will be deadlock free even when the design is using a mixture of IPs with coherent and non-coherent memory access requirements.
Once a NoC design is created, NocStudio creates as its output synthesizable RTL, verification suites, and information used by physical design to handle placement of the NoC components to meet timing requirements and manage clock skews. It also produces the documentation required to meet the ISO 26262 standard, including a safety manual for the IC.
NocStudio is already used by the #1 and #2 IC suppliers for autonomous vehicles and hyperscale computing as well as top vendors in artificial intelligence, virtual reality/augmented reality, and real-time security analytics. On April 5[SUP]th[/SUP], NetSpeed also announced that they signed a multi-year license agreement with Sunplus Technology for NetSpeed’s Orion on-chip network IP. Sunplus is a leading provider of multimedia IC solutions and automotive infotainment solutions and will use NetSpeed’s IP to accelerate the design and development of future generations of its automotive SoCs
This is impressive technology and I believe we will be hearing more from NetSpeed in the future. NetSpeed Systems is a company to keep your eye on especially as the autonomous vehicle market takes off.
See also:
– NetSpeed Systems web page
– Sunplus Technology Licenses NetSpeed’s Orion IP
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