Lora Ho is a long-time senior executive at Taiwan Semiconductor Manufacturing Company (TSMC). She currently serves as Senior Vice President of Human Resources and has chaired the company’s ESG Committee since 2011, overseeing talent strategy and corporate sustainability across TSMC’s global operations. Previously, she… Read More
Dr. Atsuyoshi Koike is the President & CEO of Rapidus Corporation, Japan’s advanced-logic foundry initiative targeting commercialization of 2-nm gate-all-around (GAA) technology later this decade. A veteran of Japan’s semiconductor industry, Koike is known for linking bold process roadmaps with pragmatic factory… Read More
Semiconductor Hardware Security Assurance is the discipline and set of practices used to build justified confidence that an integrated circuit and its supporting hardware behave only as intended, resist realistic attacks, and can be trusted over their life cycle. It combines threat modeling, secure architecture, secure … Read More
XTCO (Cross-Technology Co-Optimization) is a holistic methodology that coordinates multiple layers of technology and design—devices, interconnect/BEOL, 3D integration & packaging, architecture, and system/software—to deliver target PPAC (performance, power, area, cost) plus reliability and time-to-market.… Read More
Chip-on-Wafer-on-PCB (CoWoPCB) is a heterogeneous integration flow in which bare dies (“chips”) are first assembled and interconnected at wafer scale (on an interposer or fan-out carrier). The completed wafer-level module is then finished with board-pitch I/O and mounted directly to a printed circuit board (PCB)—eliminating… Read More
Chip-on-Panel-on-Substrate (CoPoS) is an advanced packaging architecture that “panelizes” the classic chip-on-carrier flow. Instead of building redistribution and interposer structures on round wafers, CoPoS forms them on large rectangular panels, then mounts the finished module onto an organic or glass package substrate.… Read More
A Complementary FET (CFET) vertically stacks the n-FET and p-FET of a CMOS pair on top of each other (often as stacked nanosheets), collapsing the lateral n–p spacing in today’s standard cells. By “folding” CMOS into the vertical dimension, CFET targets major area and routing wins at future logic nodes while preserving strong … Read More
Masayoshi Son (孫 正義; born August 11, 1957) is a Japanese entrepreneur and investor, best known as the founder, chairman, and CEO of SoftBank Group. Over four decades he has steered SoftBank from a small software distributor into a global technology holding company spanning telecom, semiconductors, and hundreds of startup investments.
Craig R. Barrett (born August 29, 1939) is an American materials scientist and business leader best known for serving as Intel’s 4th chief executive officer (1998–2005) and chairman (2005–2009). A former Stanford professor, Barrett helped turn Intel’s manufacturing organization into a repeatable, global advantage and guided
Yervant Zorian is an Armenian-American electrical engineer best known for pioneering work in design-for-test (DFT) and built-in self-test (BIST) for complex integrated circuits. He serves as Chief Architect & Fellow at Synopsys and President of Synopsys Armenia, where he has helped build one of the country’s flagship
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Intel’s Pearl Harbor Moment