Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what’s new with circuit simulation at DAC this year.

Notes

News – market is growing, RF CMOS simulation is growing
– Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
– Recent news with Lorenz (EM tool to create inductors), they’re part of Connections program
– APS RF released on year ago (Parallel in the new engine)
– RF usability improved, able to do s-parameter analysis

Virtuoso APS – continued to improve, up to 16 cores
– December 2010 now you can go distributed, across machines
– No special setup required
– Uses more tokens
– Super Threading: multi-core plus distributed processing (multi-core per box)
– Typical usage: Two machines, 4 cores per machine

UltraSim – looking at next generation technologies
– Usability and speed improvements done and planned
– New developers added
– Did a new RF model

Modeling – how to model FInFET (Tri-gate)?
– Compact Modeling group involvement

Altos – acquired library characterization company
– Integrated with them last year, especially memory characterization
– Works with either Spectre or UltraSim or internal simulator

Growth – Altos had 11 out of 20 top semi companies for library characterization
– Good collaboration over past 12 months too (Jim Mccanney)

Spectre – New in last year is APS and distributed
– Shares models with UltraSim

AMS Designer – transistor simulation plus HDL
– Real number modeling (standard part of SystemVerilog) lets you model analog effects in a logic verification environment
– Did a paper at the ARM conference last year, DVCON this year (assertions plus real number modeling)
o Help ADC test bench verification
– Adoption of real number modeling is driven by the design style more than the technology
– Work with designersguide.com on training the next generation of AMS designers, classes tailored to the client and offer consulting services
– Knowlent went out of business as Analog Verification IP (too limited of an approach, not portable)
– How to influence the next generation, Universities

Parasitic Aware Design – simulation with real parasitic, as early as possible in the flow
– Quickly go from schematic to layout to extracted parasitic, better simulation results
– Virtuoso can help manage the whole parasitic flow

IMS Chips (Germany) – Used Custom Designer, then went back to Virtuoso (Feb 2011)

Wolfson (UK) – Uses SNPS digital tools, and internal analog tools. They evaluated Custom Designer but choose Virtuoso plus digital flows.

Summary
Cadence has plenty of competitors in the circuit simulation space so they continue to update and innovate their tools to stay current. Only three vendors offer an integrated co-simulation between SPICE and a widely-adopted HDL simulator (Cadence, Mentor, Synopsys).

Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

Notes

Why do this?
– Reduce leakage
– Increase gate lengths on paths with slack
– Recharacterize cells for change channel length, new performance
– Take the output from Primetime for paths with slack
– Our tool also has a timing engine built into it
– Fine grain optimization for leakage optimization
– Our tool does more cell swaps than other tools do
– Can swap multi vt cells as well
– TSMC has four Vt choices, but with gate biasing you have finer control than just swapping Vt
– Gate biasing doesn’t require another mask
– Optimize for: Performance, leakage, costs
– At 28nm the PowerTrim libraries should become more mainstream
– At 40nm, you can bias the gate length to optimize as well
– Another technique for 28nm is to start with 35nm then use gate biasing
– Customers can ask for design services from Tela, or ask TSMC to use PowerTrim
– Customers: LSI Logic, Melanox, undisclosed (over 50 tapeouts so far)
– Gate biasing can make the device go faster (more leakage) or slower (less leakage)

Summary
If you fab with TSMC and want to reduce your leakage currents, then consider the PowerTrim library approach.

Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired by Cadence, spun out in 2007)
– R&D in Beijing and Silicon Valley
– NanoDesigner (4 years old): SPICE tool, not Fast SPICEo Compete with: Spectre, FInesim, HSPICE
o Accuracy is the goals
o Statistical SPICE (Monte Carlo technique)
o Customers: Not disclosed
o Pricing: Not disclosed
– IR/EM Verificationo Partnership with Grid Simulation Tech
o Customers: Not yet
Summary
I hadn’t heard of Proplus before last week, so I’ve added it to the list of all SPICE tools on our wiki page.

Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.

Daniel Borgraeve (on right)

Notes
Edxact
– Started seven years ago
– Fifteen people in the company
– Based in France
– Jivaro: RLCK reduction (RLCC) with user control of results
o Many algorithms to choose from
o Used by Aglient in their GoldenGate tool (RF Simulator)
o Used by Intel
o About 25 customers world wide (Asia, Japan, Korea, US)
o Part of TSMC AMS Reference flow 2.0
o Pricing starts at $100K per license per year

– Comanche:
o Read parasitic
o Create R values point to point, calculate delays
o CAD developers can compare two netlists (Golden versus some extraction tool)
o Parasitic analysis platform
o Used by: AMD, ST Ericsson
o Pricing starts at $100K per license per year
– Partners
o Altos (Library Characterization, used Jivaro)
o Cadence (Integrated into Virtuoso)
o SpringSoft (Integrated into Laker, can annotate parasitic into Laker)
o Mentor (read DSPF, Eldo formats)
o Synopsps (support Star RC and HSPICE syntax)
o TSMC – part of AMS Reference flow
– Runs on: Solaris, Linux, Mac

Summary
If you want more control while reducing RCLK netlists then consider looking at Edxact tools.

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.

Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank schematic, enter new design
o Read any native OA schematic
o See all the MOS instances in a tree, define layout constraints very quickly
o Drag and drop constraints
o Cross probe between MOS list and Schematic view
o Hierarchy supported
– Helix First Look
o Schematic and Analog constraints in, layout out
o Find in netlist common bulks, get placed together
o Easy way to create initial layout constraints, does auto grouping of layout
– New customers: Marvel
– 28nm migration is important, Helix is an easier way to conform to new design rules
o Auto placement helps on minimum rules
o Read design rules for density and Helix can push transistors apart to reach the rules
– Create many alternative layouts, Extract a netlist, use Calibre parasitics, create fully extracted netlist ready for Berkeley AFS
– Users: Initially the Circuit Designer starts, then handed off to the Layout Designer for completion
– Routing Example: pattern based constraints used, then autoroute between all the rows and columns of placed Devices
– New way to create layout constraints, based on patterns or Python scripts (mostly CAD or Circuit Designers create scripts)

Summary
Ciranova Helix is a tool that can create analog layout using PyCells very rapidly by a Circuit Designer. Demanding IC designers from the largest semiconductor companies in the world use these tools.

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.

Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
– New for 2011: 3D Floor planner
o Mostly a manual process to do TSV on two or more stacked dies
o 3D Floorplanner automatically finds all thos places
o Autoplace 3D vias (placed on edges in this demo because of density of SRAM on top of processor)
o Demo with 3 stacked die, also autoplace 3D vias
o Tezzaron – customer using Max 3D, designing 3D stacked wafer designs. Doing a 7 stacked chip design.
o 3D DRC – Magma has a tool, you can launch Magma inside of Max-3D and view the results interactively
o Pricing:?

OA – we can read and write it

Large designs – Virtuoso cannot move or work on the largest designs, so it’s time to consider using Max or Max-3D

Max – demo with 1 trillion MOS devices at DAC this year
– Tezzaron read in 100GB GDS II layout database into Max

Customers – Most will not be mentioned because of corporate policy.

Summary
We all know that the big three EDA companies have IC layout editors (Cadence, Synopsys, Mentor) but this lesser known EDA company has capacity and 3D features that I don’t see anywhere else.