RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
Semiconductor Expert Forum

Posted on

Should ARM care about MIPS acquisition?

Should ARM care about MIPS acquisition?
by Eric Esteve on 11-06-2012 at 3:09 am
Categories: Arm, Imagination Technologies, IP

It was not really a surprise to learn that, finally, MIPS have been sold, as the company was officially for sale since April 2012. Nevertheless, the interesting part of this news comes from the buyer’ identity: Imagination Technologies. Imagination is an UK based company, like ARM, selling processor IP cores, like ARM, but the (huge) difference was coming from their port-folio: Imagination only sales Graphic Processing Unit (GPU) IP cores, when ARM sell both CPU (the Cortex family) and GPU (MALI family), as well as Libraries and some Interface IP like DDRn Controller. Should we mention that ARM CPU IP cores are ultra-dominant in the mobile application like smartphone, media tablet, and any kind of wireless phone? I have heard about ONE design-in of MIPS CPU IP in this mobile multi segments, one out of hundreds. On the other hand, Imagination has seen a very good penetration of the PowerVR family of GPU in these mobile segments, even if MALI GPU IP had significantly increase penetration in 2011, but not at the level of PowerVR GPU IP.

In summary, in the mobile segments, you need two essential pieces, the CPU and the GPU IP cores, to build and Application Processor, as well as several dozens of other IP functions, but that’s not the topic of today. ARM is ultra-dominant with the Cortex CPU IP family (A9, A15 and now the big-little A57-A53 dual cores), when Imagination Technologies is dominant (but not “Ultra”) with the PowerVR GPU IP family, both addressing various market segments and application (smartphone, media tablet, set-top-box, HDTV… to name a few), the most lucrative being, by far, the mobile segment, with smartphone shipments forecast being in the range of 680 million units for 2012 and media tablet in the range of “only” 100 million (plus) units for 2012.

When ARM is attacking Imagination Technologies best seller product GPU IP core, with MALI family increasing penetration, that’s a threat for Imagination. But when Imagination Technologies buying MIPS and the related CPU IP cores product line, is it really a threat for ARM? If we look at the customer installed base, especially in the mobile market, we don’t expect the Qualcomm, Apple, Samsung and others to move to MIPS CPU in the short or even mid term. They could use MIPS in the license or royalties price negotiation with ARM, but changing architecture would be a highly risk bid… and what could be the benefit? Saving a few, or even a dozen million dollar is not a good enough reason to put such profitable product lines at risk, for these already installed and making good money in the mobile segments.

But, for the numerous new comers, most of them being based in China and attacking the largest mobile market (in units) worldwide, if ARM CPU IP core is certainly the most attractive solution, the cost of ownership could be a good enough reason to move –or to start- with MIPS core. As soon as their installed product base, and the related million lines of S/W developed, is not too large, they could decide to take a chance and select MIPS… Imagination will be able to address both the CPU and GPU IP cores needs, and grab some market share in various segments, nevertheless, considering how wise the company development was so far, ARM will certainly build the proper strategy to address this new deal, like they did in the past when fighting with MIPS. If you’re not convinced, just look at where MIPS has fallen today!

From Eric Esteve– IPNEST

Posted on

Waiting or EUV – Another View on the ReRAM Roadmap

Waiting or EUV – Another View on the ReRAM Roadmap
by Ed McKernan on 11-05-2012 at 9:03 pm
Categories: IP

It is ‘Quarterly’ financial report time for many companies and one can occasionally find some interesting snippets in the transcripts of the calls which normally accompany these announcements. For example, SanDisk appear to have an encouraging quarter, reversing sales declines seen through Q1 and Q2. However, what caught my eye was this quote attributed to SanDisk’s CEO Sanjay Mehrotra “We also believe that 3D ReRAM will not start production until sometime beyond 2015 given its need for EUV lithography, which is still in development phase.” (A similar comment is buried in the presentation made by SanDisk at their Analyst’s day in February this year.) This is somewhat more conservative than other company’s roadmaps as we have discussed at ReRAM-Forum.com. Coincidentally the annual EUV Lithography Workshop has just been held in Hawaii in June and the more recently, the EUV Source Workshop held in Dublin in October. Both the EUV Workshops have full proceedings on-line at www.euvlitho.com. In a bit of a departure from our regular Blog focus, we have taken a look at EUV as it appears to be a key factor in the ReRAM roadmap of at least one major memory company. For more information go over to www.ReRAM-Forum.com.

Posted on

Gustafson on Parallel Algorithms

Gustafson on Parallel Algorithms
by Paul McLellan on 11-05-2012 at 4:54 pm
Categories: EDA, Events

At the keynote for ICCAD this morning, John Gustafson of AMD (where he is Chief Graphics Product Architect as well as a Fellow) talked about parallel algorithms. Like Gene Amdahl, whose law states that parallel algorithms are limited by the part that cannot be parallelized (if 10% is serial, then even if the other part takes place in zero time, the maximum speedup is 10X), Gustafson has a law named after him. It basically says Amdahl is wrong, that there is no limit to the speedup you can get as long as you increase the size of the problem along with the number of cores. So his talk was a look at whether there are embarrassingly serial problems, problems that are not open to being parallelized.

For example, at first glance, calculating the Fibonacci series look like one. Each term depends on the previous two so how can you bring a millions servers to bear on the problem. But, as anyone who has done any advanced math knows, there is a formula (curiously involving the golden ratio) so it is straightforward to calculate as many terms as desired in parallel.


By 2018 we should have million server systems each doing teraflops through highly parallel operations running on GPUs. The big challenge is the memory wall. For operations that involve a high ratio of work to decision making, this sort of SIMD (single instruction, multiple data) can significantly reduce wattage per teraflop.


Throwaway line of the day: with great power comes great responsibility…and some really big heatsinks!

An instruction issue consumes around 30 times more power than basic mutiply-add operations and a memory access much more power than that. Memory transfers will soon be half the power consumed and processors are already power-constrained. Part of the problem is that hardware caches are very wasteful, designed to make programming easy rather than keep power down. They minimize miss-rates at the cost of low utilization (around 20%). Even more surprisingly, only 20% of the data written back out of the cache is ever accessed again so didn’t really need to be written back at all. John felt that at least for low-level programmers we need a programming environment that makes memory placement visible and explicit (as it apparently was on the Cray-2).


There are two ways to associate a SIMD GPU with a processor: on-chip and a separate off-chip device. On chip seems to work best for problems where data re-use is 10-100 (such as FFT and sparse-matrix operations) and an off-chip device works best for data re-use in the 1000s, such as dense matrix and many body dynamics.

We also need better arithmetic. Most programmers have never studied numerical analysis and so have no idea how many bits of precision there are or how to calculate it. A specific problem is that accumulating results (by adding) needs much more precision that is used to calculate the numbers to add. Eventually you are adding small numbers to a number that is so large that it doesn’t change. John had a few examples where he was using 8 bit floating point (yes, really. 1 sign bit, 3 bits of exponent and 4 bits of mantissa) but doing accurate analysis.


John’s final conclusion: if we really cherish every bit moved to and from main RAM then we can get better arithmetic answers (provable bounds) and as a side-effect help the memory wall dilemma and always have a use for massive parallelism.

Posted on

16nm FinFET versus 20nm Planar!

16nm FinFET versus 20nm Planar!
by Daniel Nenni on 11-04-2012 at 8:10 pm
Categories: FinFET, Foundries, TSMC

The common theme amongst semiconductor ecosystem conferences this year is FinFETS, probably the most exciting technology we will see this decade. A lot has been written on SemiWiki about FinFETS, it is one of the top trending search terms, but there is some confusion about the process naming so let me attempt to explain.

In planar process technologies the 28nm or 20nm implies the minimum transistor gate length of 28nm or 20nm. Corresponding to that lithographic capability are two other critical dimensions: the “contacted gate pitch” and the “metal pitch” for the lowest, thinnest metal layers. (Higher metal layers will be thicker with less resistance which are more suitable for longer routes but will have a greater width+space design pitch.)

Given that, the 16nm FinFET process technology is a bit of a misnomer. It was probably named by Marketing people to imply that the resulting performance when transitioning from planar to FinFET in a 20nm lithography process would be “between 20nm planar and 14nm FinFET”.

Why 16nm FinFETS you ask? Two reasons: (1) EUV is late so a true 14nm FinFET process will not be possible by 2015 and (2) Customers designing mobile devices were not willing to wait for the power savings FinFETS have to offer. As a result, the current 20nm lithography process was modified for FinFETs, and the 16nm FinFET process was born.

If you were to ask, “What is the minimum gate length, contacted gate pitch and metal pitch for 16nm FF, and how does that differ from 20nm SoC?”, you would get the answer that it’s the same litho design rules, just a different transistor structure.

There is one additional measurement that is introduced in a FinFET technology: the effective device width per micron. These are transistor parameters, and they are an indicator of performance, but they are relatively independent of the contacted gate pitch + metal pitch, which define the achievable circuit density.

The IBM 14nm FinFET tape out briefing provided some interesting process details. Disclosing this type of information is certainly not IBM-like so the stakes are obviously high in the race to FinFETs:

[TABLE] align=”left” style=”width: 470px”
|-
|
| 32nm
| 28nm
| 20nm
| 14nm
|-
| Architecture
| Planar
| Planar
| Planar
| FinFET
|-
| Contacted poly pitch
| 126nm
| 114nm
| 90nm
| 80nm
|-
| Metal pitch
| 100nm
| 90nm
| 64nm
| 64nm
|-
| Local interconnect
| No
| No
| Yes
| Yes
|-
| Self-aligned contact
| No
| No
| No
| No
|-
| Strain engineering
| Yes
| Yes
| Yes
| Yes
|-
| Double patterning
| No
| No
| Yes
| Yes
|-

Bottom line, lithographically, both 16nm and 14nm FinFET processes are still effectively offering a 20nm technology with double-patterning of lower-level metals and no triple or quad patterning.

One team has chosen to define the performance of their FinFET as a “half node” improvement (e.g., 20nm ->16nm), whereas the other has chosen to represent the performance of their FinFET as equivalent to a “full-node shrink” (20nm -> 14nm). There will be slightly different fin_height, fin_thickness, and fin_pitch parameters between the two processes but the circuit density is really still the same as 20nm.

Some designs might be smaller but in general I think FinFets at 16nm and 14nm will offer significantly lower power consumption and leakage but only marginally better performance and area than 20nm planar, just my opinion of course.

Who do you think will be first to get FinFETS into volume production? Would it be TSMC, Samsung, or GF? Check out the SemiWiki FinFET poll HERE. Anybody can vote so please do.

Also see:

GLOBALFOUNDRIES 14nm FAQ

FinFET Wiki

Posted on

Chip On Wafer On Substrate (CoWoS)

Chip On Wafer On Substrate (CoWoS)
by Daniel Payne on 11-03-2012 at 5:19 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

tsmc cowos test vehicle1

Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform there was a presentation from John Park, Methodology Architect at Mentor Graphics called –A Platform for the CoWoS Reference Flow. Continue reading “Chip On Wafer On Substrate (CoWoS)”

Posted on

Electromigration (EM) with an Electrically-Aware IC Design Flow

Electromigration (EM) with an Electrically-Aware IC Design Flow
by Daniel Payne on 11-03-2012 at 4:05 pm
Categories: Cadence, EDA

fig2a

Electromigration (EM) is a reliability concern for IC designers because a failure in the field could spell disaster as in lost human life or even bankruptcy for a consumer electronics company. In the old days of IC design we would follow a sequential and iterative design process of: Continue reading “Electromigration (EM) with an Electrically-Aware IC Design Flow”

Posted on

ARM TechCon 2012 Trip Report

ARM TechCon 2012 Trip Report
by Daniel Nenni on 11-02-2012 at 12:00 pm
Categories: Arm, IP

I must say the ARM conference gets better every year, as do the attendance numbers. More than 4,000 people showed up including 5 SemiWiki bloggers, two of which I had not yet had the pleasure of meeting.

First I have to mention my favorite vendor booth. I don’t remember what company it was but the girls in fishnet stockings giving out bottle openers were funny. I even chatted with one, a very nice lady from Ireland with a six year old daughter just trying to make some money in a difficult economy. I also saw Granny Peggy Aycinena lurking in the shadows so expect fireworks on this one. The Granny nickname comes not from her age but her bias against so called ‘booth babes” at trade shows. You may remember Peggy from the DAC 2012 Cheerleader fiasco. Funny stuff!

Back to the conference, the Keynotes were very well done and even “Apple esque”. The speakers were polished, the presentations were content rich, there were nice videos, and the intermingling of industry executives and panels from the massive ARM ecosystem was great. I sat with Paul McLellan for the most part and he writes way much more better than me do so be sure and read his ARM TechCon blogs:

ARM 64-Bit

IBM Tapes Out 14nm ARM on Cadence Flow

ARM and a LEG

Internet of Things

The last keynote (Thursday morning) was ARM CEO Warren East. Saving the best for last was a good strategy to bolster traffic on the final day. The most interesting part of the keynote was the embedded FinFET panel discussion between TSMC, Samsung, and GLOBALFOUNDRIES. Spoiler alert: TSMC’s Shang-yi Chiang stole the show! I hope the video is up soon because it was great!


The first question was on the challenges we face moving forward and Shang-Yi said, “FORECASTING!” As in the 28nm shortages this year were due to bad forecasting not yield and manufacturing delays, which is absolutely true. As Shang-Yi said, “28nm demand was 2-3x the forecast.”

Shang-Yi was the first person to talk to me candidly about the 40nm yield problems while they were happening so I have faith in what he says. He is a genuine guy who puts the “trusted” in the “Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come”.

Shang-Yi also mentioned cost as a challenge and for 20nm that is absolutely true. He also discussed the cost of an empty fab and let me tell you, there is going to be plenty of extra fab capacity next year as Samsung, UMC, and GLOBALFOUNDRIES get 28nm into full production.

The panel also discussed FinFETS which is a common theme amongst most of the conferences this year. I will blog my issues with FinFETS next but the panel response was quite funny. Shang-Yi went first and said that Chenming Hu (The father of FinFETS) worked at TSMC and TSMC has been working on FinFETS for 10+ years so no worries. Not to be out done, the Samsung guy said they have been working on FinFETS as long as TSMC and his concern was with variation which is absolutely true with the Fins. On Tuesday I was at a presentation about IBM’s 14nm FinFET test chip. Since when does IBM talk openly about stuff like that? GF also has FinFET bragging rights and had their own fireside chat at ARMTechCon talking about the “Lab to Fab Gap”:

Given all that boasting, if you had to bet today, who do you think will be first to get FinFETS into volume production? Would it be TSMC, Samsung, or GF? Remember, Intel does not use FinFETS, they use Tri-Gate transistors. 😉 Check out the SemiWiki FinFET poll HERE. Anybody can vote so please do.

Posted on

Internet of Things

Internet of Things
by Paul McLellan on 11-01-2012 at 8:10 pm
Categories: Arm, IP

Another announcement from the Warren East’s ARM keynote this morning was the creation of a SIG within Weightless, which is an organization responsible for delivering royalty-free open standards to enable the Internet of Things (IoT). The SIG is focused on accelerating the adoption of Weightless as a wireless wide area global standard for machine to machine short to medium range communication. The founder companies are ARM, Cable and Wireless Worldwide, CSR (formerly Cambridge Silicon Radio) and Neul.

As Warren pointed out in his keynote, if you are very local there are a number of good standards such as WiFi and Bluetooth that you can use for wireless connectivity. If you are outside and want to go over 100m, say, then pretty much you have to use cellular technology such as GSM, CDMA or LTE. The trouble with that is that it is optimized for human communication such as voice or surfing the net and as a result it is very time and power intensive and the batteries don’t last long (think months).

Weightless operates in the whitespace being freed up as analog terrestial television gives back its spectrum. This turns out to be ideal for low power medium distance transmission for all the same reasons that back when TV was invented it was picked as the band: it transmits long distances at low power well, can go through wall, into basements and so on. Plus this spectrum is standard worldwide: although there are (mostly were) several different analog TV standards (NTSC, PAL, SECAM) the spectrum used for analog TV was internationally standard. This gives it a 4-10X gain in efficiency over the bands where cellular operates. The spectrum, as it frees up, is unlicensed and does not require complex antenna engineering.

For machine to machine communication, where latency is not a problem, the SoCs can sleep most of the time. Unlike cellular where you can’t wait 15 minutes for your phone call to connect (but you can wait a few seconds, I bet you didn’t know you already are doing), in applications like monitoring irrigation or power metering, this is not an issue. And the protocols can be optimized for this.

As an example of the mismatch between cellular standards, Gary Atkinson of ARM pointed out that for a smart power meter using GPRS (the data standard part of GSM) to transmit a single little bit of data (such as the current meter reading) takes 2000 packets. It is not a fair comparison, of course, but that is the point. GPRS is set up to assume you are going to want to send a lot of data in a timely manner and has a heavyweight protocol to make that happen.

The target is chipset cost under $2, range up to 10kM and a battery life of 10 years. A little different from the spec Apple is working on for the iPhone6.

The Weightless website.
Weightless wikipedia page.

Posted on

Jasper Apps White Paper

Jasper Apps White Paper
by Paul McLellan on 11-01-2012 at 7:30 pm
Categories: EDA

Just in time for the Jasper User Group meeting, Jasper have a new white paper explaining the concept of JasperGold Apps.

First the User Group Meeting. It is in Cupertino at the Cypress Hotel November 12-13th. For more details and to register, go here. The meeting is free for qualified attendees (aka users). One thing I noticed at the meeting last year was just how innovative some of the users were in how they used Jasper’s products and, as a result, how much the users learned from each other.

The white-paper covers the motivation for changing the way in which Jasper technology is configured and delivered. Historically, formal verification technology has been licensed as a comprehensive suite of tools that can be used to address a broad range of formal verification applications and problems. Such deployment required a wide range of in-depth skills on the user’s part before the technology could be leveraged by not only first time users, but also experienced ones. New users were often overwhelmed by the comprehensive nature of the technology and the steep learning curve, while experienced users wishing to deploy a narrow application scope across the organization were impeded by the all-in-one approach.

Early stage users generally prefer to adopt and deploy new design and verification methods using a low risk, step-by-step approach, which also allows them to accumulate skills and expertise incrementally. Experienced formal users are more likely to utilize focused capabilities to tackle specific issues and applications within design and verification, but must do so across an organization rather than on an individual basis. In both cases, users traditionally had to license an entire tool suite in order to access only a subset of its capability. Consequently, the all-in-one approach did not and does not provide for efficient deployment for either type of user.

Rather than deploying a general-purpose, all-in-one tool suite, many design teams need application-specific solutions that:

  • Address a wide variety of verification applications throughout the design flow, enabling them to adopt formal technology, application-by-application;
  • Enable teams to acquire the expertise necessary to address only the verification task(s) in hand;
  • Allow teams to license only the technology appropriate for a particular application; and
  • Eliminate or significantly mitigate the perceived risk in adopting unfamiliar technology.

JasperGold Apps are interoperable solutions, each of which targets an individual formal verification application. Using JasperGold Apps, design teams can adopt and expand their use of formal verification by employing a low-risk, application-by-application approach. Each JasperGold App provides all of the tool functionality and formal methodology necessary to perform its intended application-specific task, eliminating the need to license a complete formal verification suite. Each JasperGold App enables the user to acquire only the expertise necessary for the particular task at hand, eliminating the need to become expert in every aspect of formal verification.

Download the white paper from this page.

Posted on

SpyGlass IP Kit 2.0

SpyGlass IP Kit 2.0
by Paul McLellan on 11-01-2012 at 6:00 pm
Categories: EDA, Foundries, TSMC

On Halloween, Atrenta and TSMC announced the availability of SpyGlass IP Kit 2.0. IP Kit is a fundamental element of TSMC’s soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft (synthesizable) IP.

IP Kit 2.0 will be fully supported on TSMC-Online and available to all TSMC’s soft IP alliance partners on Nov. 20, 2012, just in time to make sure your turkey is SpyGlass Clean.

TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. Currently, over 15 soft IP suppliers have been qualified through the program. IP Kit 2.0 represents an enhanced set of checks that adds physical implementation data (e.g., area, timing and congestion) and advanced formal lint checks (e.g., X-assignment, dead code detection). IP Kit 2.0 also allows easier integration into the end user’s design flow and enhanced IP packaging options.

On the same subject, IPExtreme had an all day meeting at the computer history museum about, duh, IP. One of the companies presenting was Atrenta and here is a video of Michael Johnson’s presentation on IP Kit.

And, completely off topic, at the end of the IPExreme event they served wine and beer and had a short presentation on each beforehand. Jessamine McLellan, then the sommelier at Chez TJ in Mountain View (now the bar manager at the not-yet-open Hakkasan in San Francisco) gave a presentation on pairing wine with food. That last name sounds a little familiar…