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Ausdia’s Timevision

Ausdia’s Timevision
by Paul McLellan on 06-11-2012 at 8:05 pm
Categories: EDA
1 Comment

I met Sam Appleton of Ausdia during DAC. I found it quite hard to understand exactly what they do. I’ve talked before about something that I nick-named City Slickers’ Marketing. It is named after the following exchange from the movie City Slickers:Curly: Do you know what the secret of life is? [holds up one finger] This.
Mitch: Your finger?
Curly: One thing. Just one thing. You stick to that and the rest don’t mean shit.
Mitch: But, what is the “one thing?”
Curly: [smiles]That’s what you have to find out.

Sometimes this amounts to making sure that you have the right product and sometimes this means making sure that you have the right explanation and positioning. If you can’t have a good elevator pitch to a VP engineering at a customer then your product is going to be hard and timeconsuming to sell (and by the way, talking of elevator pitches, Sand Hill Road doesn’t really have elevators since there are no towers).

Ausdia has some of this latter problem. What they do, the niche they fill, is hard to explain simply. I think I get it but I’m not completely sure.

Timevision is a product used along with a static timing tool (such as Synopsys’s PrimeTime). The reality is that a modern design has tens if not hundreds of millions of instances, power down regions, multiple clock domains, scan test and more. If you don’t have a completely solid set of timing constraints, a good understanding of the clock architecture, power architecture, false paths and so on then you are going to end up with gigabytes of data that is pretty much impossible to interpret.

Timevision is a tool to address this that adds intelligence into how the static timing tool is driven. It can deduce a lot from just examining the netlist but the more information you give it the more powerful it gets and the more useful the output from STA will be. Under the hood it has formal techniques for deducing what is going on in your design without having to be told everything. So instead of having to write thousands of lines of timing constraints, they are synthesized and deduced from the design itself along with a small amount of steering information.

A particular challenge with static timing is that a lot is done right at the end of the design. Problems here don’t have any schedule flexibility to make up for time lost while closing timing for the design. So it is doubly important to make sure that you have good constraints by the time tapeout approaches.

Ausdia is a privately held company, obviously. Less obviously it has no external investors and has been completely bootstrapped. It was formed in late 2006 and started product development in 2008 (who knows what they did in 2007!) and brought their first product to market in 2010. Since then they have survived on product revenue.

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One Billion Transistor IC Layout Editing

One Billion Transistor IC Layout Editing
by Daniel Payne on 06-11-2012 at 6:33 pm
Categories: EDA

There are only a handful of billion transistor IC designs in existence today, so when an EDA company touts 1 trillion transistor IC layout editing then I take notice. This year at DAC I met with Katherine Hayes and Karen Mangum of Micro Magic to get an update on their IC layout tools. Continue reading “One Billion Transistor IC Layout Editing”

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From SPICE Netlist back to Schematics at DAC

From SPICE Netlist back to Schematics at DAC
by Daniel Payne on 06-11-2012 at 5:22 pm
Categories: EDA, Events
4 Comments

I first heard about SPICE Vision Pro when working at Mentor Graphics where we needed a way to visualize SPICE netlists and debug SPICE simulation results node by node on a design where we didn’t have the original schematics. Last Monday I met the engineers from Concept Engineering in their booth at DAC to get an update, Gerhard Angst is the CEO.


Continue reading “From SPICE Netlist back to Schematics at DAC”

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Cadence/TSMC 3D

Cadence/TSMC 3D
by Paul McLellan on 06-11-2012 at 5:16 pm
Categories: Cadence, EDA

Mark Twain remarked that everyone talks about the weather but nobody does anything about it. 3D ICs seems to be a bit like that. Over the last couple of years there have been lots of people talking about 3D but very little that has actually been manufactured. In addition to the weather, everyone talks about Xilinx’s 3D Virtex design because it is about the only one that is in manufacturing (it is so high end I hesitate to say it is “volume manufacturing”).

All of Cadence, Synopsys and Mentor have talked about some aspects of 3D in their toolsets. The challenge with 3D is that it affects everything from synthesis on down and if only a few tools have been updated it is like a ladder with missing rungs, hard to get from one end to the other of the design flow.

At DAC, Cadence announced a full suite of tools that they have been working on with TSMC to create what they are calling the CoWoS Design Ecosystem. I met with John Murphy and Samta Bansal to find out more. The first obvious question is CoWoS, what is that? It stands for chip-on-wafer-on-substrate (or sometimes on-silicon) and is TSMC’s name for their heterogeneous silicon interposer approach. Heterogeneous in the sense that all the die on the interposer do not need to be from the same semiconductor process.

As a test vehicle the designed and manufactured the first heterogeneous CoWoS module. There were 3 die: a 40nm memory, a 65nm GPS and a 28nm SoC, all put together on a 65nm silicon wafer. And it is yielding. Nobody is saying how much yet, but just as with the Xilinx part, one of the major reasons for doing this sort of design is to get the learning experience of what it takes to make an economic solution.

As a result there is now a path for 2.5D interposer-based technology through a Cadence (almost entirely) flow from implementation, to analysis, to verification and including DFT and test solutions.

The flow starts with a fairly standard implementation of the top die, obviously bumped rather than designed to be bonded out, but using standard RDL routing. Wafer test is developed (which is very important in 3D designs, lots of known-good-die get wasted when a bad die slips through wafer sort). Next the interposer is designed and routed. The interposer itself needs to be analyzed and then the whole system of interposer and die (and I’m guessing package) to check everything is correct, that IR drop is within tolerance and pulling all the test together for a package level test that can test everything

Above is the first module on the Cadence booth. They also had it on the TSMC booth — but with big signs saying no cameras or camera-phones. I think this probably just reflects different cultural attitudes to secrecy. Cadence has done several other 2.5D chips. Nobody is yet ready to announced but Cadence claim 8 testchips and 1 production chip.

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A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools

A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
by Daniel Payne on 06-11-2012 at 4:07 pm
Categories: EDA, Siemens EDA
2 Comments

Linda Fosler, Tom Daspit and Mitch from Mentor Graphics met with me last Monday at DAC to provide an update on IC layout and circuit simulation tools. My notes follow:

Overview – Pyxis for Schematic and Layout, IC Station is re-branded as Pyxis. (Pyxis schematic is still Falcon, Ample language is still used.) Continue reading “A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools”

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The Apple and VMWare Alliance Threatens Microsoft (and Fabless ARM Camp)

The Apple and VMWare Alliance Threatens Microsoft (and Fabless ARM Camp)
by Ed McKernan on 06-08-2012 at 6:00 pm
Categories: Arm, IP
7 Comments

The speed with which The Mobile Tsunami engulfs the old PC Market is just incredible. 18 months ago the tablet and smartphone markets were considered a Green Field of Opportunity for PC OEMs and chip suppliers to graze in for the next decade. The fences, however, are closing in fast as Apple continues to drive its iOS empire into new geographies and market segments. Even I thought a few months back that corporations would hedge on some of their tablet purchases by staying with the Wintel x86 legacy (I was never a believer in Windows on ARM). Now I am switching my view to the conclusion that Apple and VMWare will partner to take out Microsoft in the corporate world with their full range of iOS based iPADs through x86 and MAC OS based MacBook Air and MacBook Pro notebooks.

Founded in 1998, VMWare was one of the few startup companies to come out of the 2000 technology bubble downturn and thrive with a software product that enabled much greater server efficiency. The software products they create can easily be summed up as the efficient hardware resource allocator for a multitude of application sessions running various flavors of Linux, Microsoft and MAC O/S and their applications. For the last few years they have helped us old Wintel guys switch to the MAC while running some one off Windows programs.

During the first six years of its existence it was constantly under the threat of Microsoft destroying them by coming up with their own virtualization software. So in 2004 they sold out for $625M to EMC to alleviate the near term threat from Redmond. EMC subsequently took them public in 2007 and today they are worth $40B vs. Microsoft’s $246B. For the past few years while Facebook has gotten all the attention, VMWare has seen its stock price increase by more than three times. They are an Oasis for software engineers and are hiring like mad, including in the area of iOS development. What does this mean?

A couple weeks ago I sat through multiple Wall St. analyst pitches of which one was focused on the coming corporate transition from Windows XP (remember that one – yea the one introduced when your Father was still driving an Oldsmobile) to Windows 7. The analyst described with a pained look on his face how corporate IT hates to go through the typical transition that requires them to check out every PC and see if the new OS will operate without breaking or whether to ditch it for a new machine. It’s expensive and time consuming to say the least.

Apple knows that corporations are facing two trends today that work in its favor. The first is the BYOD (Bring Your Own Device) to work (usually an iPhone and MacBook PC) and the second is the strong interest in the iPAD. Apple needs just one more trick to get the CIO to buy in to the Apple ecosystem and that is support for the Windows Legacy. This is where VMWare comes in to save the day. Their current software will allow an Apple MAC to run Windows sessions. I am speculating that when it comes to iPADs, VMware is going to offer a piece of code that sits on top of the ARM processor to allow Windows sessions that are delivered from the iCloud to the device. Remember that the iPAD has very little in the way of DRAM so the cloud is the way to go and this is Apple’s way of getting corporations to move their enterprise to its iCloud. Nice lock in strategy.

Microsoft has apparently woken up and is rumored to be announcing an iOS version of Office in November (Android versions are probably on the backburner as Microsoft is trying to use x86 tablets and smartphones to win corporate and keep Google out). This may sound confusing because on the one hand, Microsoft’s primary revenue comes from Windows based PCs running Office. On the other hand they see Apple assaulting corporate America and they must save Office, their biggest revenue generator, even if it means losing a Windows 7 or Windows 8 license. It’s the lesser of two bad choices.

The ramifications of this Apple and VMWare partnership will reverberate across the semiconductor industry. First and foremost, the Microsoft’s large $246B market cap is now to be carved amongst Apple, VMWare and Intel. Intel will continue to own Apple’s Mac business and soon will fab Apple’s ARM processor. ARMH continues to win through Apple but loses license and royalty revenue from the rest of the mobile ARM Camp that was looking to take a piece of the Green Fields. With a solid corporate strategy, it will be difficult for HP and Dell to stop the Apple Mobile Tsunami. The tide has definitely turned from the time just 18 months ago when it looked like the Fabless ARM Camp in partnership with Microsoft and Google was going to thrash Intel in PCs.

Full Disclosure: I am Long AAPL, INTC, QCOM, ALTR