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New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.
by Eric Esteve on 10-04-2012 at 8:10 am
Categories: Cadence, IP

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

Gabriele ZARRI, Moshik RUBIN, Cadence
Sophia Antipolis, France SAME 2012 Conference – October 2 & 3, 2012 2

Abstract:

With more than 50% of the world‟s population using cellular phones and the growing number of devices that go mobile, from game consoles and media player to tablets and smartphones, the demand for higher bandwidth, less power consumption and, of course, reduced cost – led a consortium of companies to form the MIPI Alliance. The goal of the MIPI Alliance is to define a suite of interfaces for use in mobile and consumer products, covering all the different aspects including Battery signalling (MIPI BIF), Radio (MIPI DigRF and RFFE), Digital audio (MIPI SLIMBus), Off-die memory sharing capabilities (MIPI LLI), Camera sensors (MIPI CSI) and Displays (MIPI DSI).

Most of those protocols use common layers (like Unipro and/or M-PHY) that guarantee a consistent interface that enables RTL reuse and optimization. Pre-silicon Verification of MIPI complaint devices is challenging and demanding; the layered structure of the specifications and the rapid pace of new revisions and features require a flexible, modular and advanced testbench which is well beyond the ability of the traditional directed testing verification scheme that most designers employ.

This paper will present an advanced verification methodology and offer some practical guidelines for pre-silicon verification of MIPI devices. Real-world verification environments used in actual verification of MIPI devices will be reviewed. The mobile market requirements are expanding quickly in terms of performances for battery duration, bandwidth needs, video capabilities like 3D, etc…

The goal of the MIPI Alliance is to define a suite of interfaces for use in mobile and consumer products, covering all the different aspects including Battery signalling (MIPI BIF), Radio (MIPI DigRF and RFFE), Digital audio (MIPI SLIMBus), Off-die memory sharing capabilities

(MIPI LLI), Camera sensors (MIPI CSI) and Displays (MIPI DSI).

Most of those protocols use common layers (like Unipro and/or M-PHY) that guarantee a consistent interface which enables RTL reuse and optimization Old standards needed to evolve in order to enable the new market requirements. CSI-2 protocol, targeting camera interfaces, was one of the first MIPI to be well adopted by the IC developers but was based on a PHY that could support up to 1Gpbs per lane ; now with increased bandwidth requirements, a new version of the protocol (CSI3) was created in order to leverage Unipro layered approach over a new phy (MPHY) that can support up to 6Gbps per lane with a reduced number of wires.

Since we are now moving towards multiple videos flows merging into the same screen, exploding the current video performance capabilities, the display protocol (DSI-2) is currently following the same trend and will soon be able to connect to Unipro/MPHY layers as well.

The attractive performance and the robust implementation of the MIPI protocols have now gone beyond the MIPI family boundaries and we can see other standards bodies taking advantage of MIPI protocols, layering application driven protocols on top of MIPI Unipro and/or M-PHY. The recent examples are JEDEC‟s UFS flash memory, implemented on top of MIPI M-PHY, and SSIC (Superspeed Inter-Chip), enabling USB 3.0 on top of MIPI M-PHY.

This fact introduces the needs of advanced flexibility in the protocols, which now have to be interfaced with other industry standards, making the number of possible interfaces configurations even wider. Now with such tight requirements something else becomes urgent: improving cost and resources sharing across dies.
For example, phone memories are not fully used within the same chip and until now every dye had to have its own leading to a much un-optimized implementation and higher cost.

One of the newest protocols of the MIPI family, is a low latency interface (LLI) which allows an off-die memory sharing between a processor chip and a companion one, guaranteeing that the same memory could be accessed from off-dye and therefore sparing the cost of additional memories by fully reusing the same among chips.

As its “big brother” Unipro, LLI is using as well the M-PHY protocol as a physical layer.
This makes M-PHY protocol a well established new standard for general purpose chip-to-chip interface.
The introduction of many, new and advanced specifications, with high dependencies between them, brings along new verification and testing challenges that traditional pre-silicon verification techniques cannot address.

In order to keep up with the latest standards, mobile SoC and systems manufacturers need solutions that can test the functionality of their designs―quickly, accurately, and cost-efficiently. Pre-silicon Verification of MIPI complaint devices is challenging and demanding; the layered structure of the specifications and the rapid pace of new revisions and features require a flexible, modular and advanced testbench which is well beyond the ability of the traditional directed testing verification scheme that most designers employ.

In a layered-protocol verification IP, the major challenge is the ability to provide enough flexibility from the upper layers without reducing the effectiveness of the random approach. In a typical example, if IP developers are interested in a standalone verification of every and each layer of their IP, their activity might be heavily impacted as the protocols pile up : an MPHY verification engineer requires the ability of generating all kind of traffic on the physical lanes, which will guarantee a full coverage of the protocol, including error injection mechanism to guarantee enough robustness. But based on the upper layer used on top (LLI, Unipro, DigRF), the kind of K-symbols required, the width of the symbol, the physical transmission mode might change. The challenge for a VIP developer in this case would be to provide a multi-purpose verification IP capable of containing all kind of configurable implementation fitting all user models.

When using this same PHY under Unipro, the verification activity will actually depend on the confidence of the MPHY IP itself. Unipro protocol contains many layers, that go from the Physical Adapter(PA), to the Data Link Layer (DLL), to the Network Layer (NL), up to the Transport Layer (TL). On top of it, we can position the Application Layer, which can consist, for example, in the camera layer (CSI-3).

The suggested verification approach would be bottom –up, i.e. starting from the Physical Adapter layer ;
The major features that could be verified would be, for example, the link startup, the link configuration (and re-initialization), and correct sending/reception of PACP frames. Once this layer is correctly verified we can move to the next one, which will focus mostly for all classes of traffic on Flow control, arbitration schemes, data AFC and NAC transmissions.

While the verification of the NL would focus on the DeviceID information, and to send/receive the packets (with short and long header), the TL verification would address the connection management for multiple ports (C-Ports), the address translation, the flow control when present (end-to-end flow control (E2EFC) or CSD), and the segmentation/reassembly.

If every layer has its own specificities and could be verified only focusing on its own features/capabilities, it would be interesting to be able to control from an upper layer, like the TL, all kind of items belonging to the NL and the DLL layers.

If from a verification IP a random generation of a TL segment will take care of pseudo-randomizing all the rest of the layers traffic down to the MPHY symbols (according to the upper layer constraints and the protocols‟ specification), there is often the need of fully controlling the scenario which is going to be generated by the Verification IP : a simple reason might be the DUT readiness, as during the development phase some functionalities might not be implemented yet, and a more „direct test‟ approach might be required.

But if this is an easy task with a limited number of parameters in a single-layered protocol, in our example it is not easy to know in advance if a control of the MPHY capabilities is required from a Unipro TL, or if a control only on the direct layers beneath him (NL and DLL) will be enough.

This verification choices are often dictated by the confidence of the modules verification : if an MPHY IP is verified in-house by a team sit right next door, the verification engineer will be more confident than if the IP has been purchased by a third party over which he didn‟t have visibility during the IP level verification.
The same rationale applies to other protocols, like LLI. When the LLI receives an error from the MPHY, it‟s supposed start a retransmission mechanism. During the LLI IP verification (pictured below as LLI Device Under Test) the traffic is generated by LLI TL layer.

Now, there are many MPHY errors that can be the source of the error signal toggling from the MPHY up to LLI layer parallel interface. The only way of testing the retransmission from the LLI protocol stack is to inject traffic from the TL-layer while controlling the MPHY error generation.
It is clear that in a layered verification activity, the only way to guarantee a full coverage is to provide to the users a way of controlling all layers, which makes a VIP user interface extremely complete and therefore complex to create in a easy-to-use manner.
The purpose of the article was to give an overview of emerging MIPI standards, with focus on advanced pre-silicon verification methodologies and techniques to test MIPI protocol compliance, providing practical guidelines for pre-silicon verification of MIPI devices.

Moshik Rubinis Senior Product Line Manager for Verification IP (VIP) at Cadence. He has been in the EDA industry for over ten years. He served as Verification IP Engineering manager at Verisity and now manages several protocols within Cadence’s VIP portfolio including PCIe, HDMI and MIPI verification IPs. Mr. Rubin holds a BS in Computer Engineering from the Technion – Israel Institute of Technology as well as an MBA from Tel-Aviv University’s Recanati Graduate School of Business.
Gabriele ZARRI
Gabriele Zarriis a Verification IP Solutions and Deployment Architect, in charge of OCP and MIPI product deployment worldwide and responsible for Cadence’s VIP portfolio deployment for Europe. He has been in the EDA industry for ten years serving different positions in Project and Product Management for Verification IPs.
He is currently chairing the Functional Verification Working Group for the OCP International Partnership (OCP-IP).
Mr. Zarri holds a MS in Electronics and Telecommunications from the Sophia-Antipolis University.

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So British! with Mike MULLER (ARM CTO & Founder) at SAME Conference

So British! with Mike MULLER (ARM CTO & Founder) at SAME Conference
by Eric Esteve on 10-04-2012 at 5:36 am
Categories: Arm, Arteris, IP

SAME conference has started with Joel Huloux, Chairman of the MIPI Alliance, who gave a high level introduction about MIPI, rather business than technology oriented, talking to Marketing/Management audience. Extracting the main points from his presentation:

  • More than 30 specifications have been issued (Important remark: a MIPI protocols is NOT a standard, like can be PCI Express or SuperSpeed USB)
  • About 250 companies are part of the Alliance, that is, the organization can rely on 5000 members (Engineers) to define and write the specifications. That’s a pretty large engineering resource!
  • Contributors list includes now the main S/W players, Apple, Google and Microsoft (you can see contributor list below):

The next presentation, about MIPI Low Latency Interface (LLI), was from Philippe Martin, CTO at Arteris. We already have talked about LLI in Semiwiki in detail, see here, but this technical presentation will certainly provide more precise information to the reader. If we need to summarize, let say that LLI is a packet based, layered communication protocol, including PHY Adapter (PA), Data Link (DLL) and Transaction (TL) layers, for the Controller (the IP sold by Arteris), interfacing with a MIPI M-PHY (PHY IP sold by Synopsys, cosmic Circuits et al.). Any IP need a Verification IP (VIP), isn’t it?

I don’t know if Cadence and Arteris have synchronized, or if these companies are simply addressing hot topics, but this presentation from Gabriele Zarri, MIPI Verification Architect with Cadence, was effectively completing the LLI IP presentation. From an article by Gabriele Zarri that you can read here on Semiwiki, we understand what makes MIPI VIP not so easy to manage is the layered structure of the specification: “…But if this is an easy task with a limited number of parameters in a single-layered protocol, in our example it is not easy to know in advance if a control of the MPHY capabilities is required from a LLI TL, or if a control only on the direct layer beneath him (DLL) will be enough. … It is clear that in a layered verification activity, the only way to guarantee a full coverage is to provide to the users a way of controlling all layers, which makes a VIP user interface extremely complete and therefore complex to create in a easy-to-use manner.”

Before going to listen to Mike Muller, it was time to have a break, and I took the opportunity to meet with Franz Dugand and Ange Aznar, founders of RivieraWaves on their booth. There was a nice demo on the table: their WiFi 11n MAC IP and Modem IP, each loaded in Virtex 6 FPGA (one FPGA per IP as the modem complexity can go up to several million gates depending on the MIMO configuration!) emitting through an external RF to send a movie to a PC, the sound being transmitted by their Bluetooth IP. Impressive and efficient, as it’s always good to have Silicon to show when you want to demonstrate an IP!

I know Franz and Ange since the time they were working at Wipro, and I am appreciative: when Wipro decided to close the Sophia-Antipolis site, dedicated to wireless IP design and sales, they decided to take the challenge, and started Riviera Waves, focusing on what the market was expecting (in their opinion): Bluetooth (and WiFi) MAC and Modem IP design for low power. It seems that designing for low power was a pretty good idea, as they are not only still alive, but growing! They have written an award winner paper, it can be downloaded here: “Power / Energy Simulation tool for connectivity systems”, getting the Best Paper Award at SAME 2011.

But it’s time now to attend the Keynote talk from Mike Muller, ARM CTO, “A 2020 View & Perspective”. The conference room is now absolutely full, it’s magic to see how just mentioning “ARM” can be efficient. We all felt lucky to listen one of the founders of a company becoming the major threat for Intel, on top of being THE successful IP vendor, and by far!

As many of us, Mike Muller has started to design ASIC, except that this was in 1983-85 and that one chip could be completed by a single man within a year or even less. At that time, he was working for Acorn Computer and the company was selling PC-like, except that the core processor was already a Reduced Instruction Set Computer (RISC), in fact it was the first version, 3000 gates large (!), of the ARM CPU family. VLSI Technology produced the first ARM silicon on 26 April 1985. Then, in 1990, the work was so important that Acorn spun off the design team into a new company called Advanced RISC Machines Ltd, and Mike Muller was part of the founding team. Answering to a question about the attractiveness of engineering career for young people, Mike said that the geek, considered as a sad guy about 10 years ago, is, nowadays, seen as a lot more attractive, as he can make million dollars when successful! That’s certainly true for him, by the way.

Mike has also shared with us some investigations he has made on the so call “productivity gap”. The results are very interesting! When you compare ARM1 (3K gates), designed in 1985, with Cortex M0 (8K) designed 20 years later, you see that:

  • Moore’ law is almost respected, Cortex M0 (designed in 28nm) occupying 1/10,000 of ARM1 area, designed in 2um
  • the productivity, expressed in (computing power)/(design effort in man month) has increased more than comparing productivity of S/W development on the same period
  • in fact, the most worrying effect comes from the power consumption: if, in term of MIPS, Moore’ law works OK, the power consumption did not decrease, and by far, as it could have done.

A person who has kept in mind all the data related to microprocessor chip design can give you a unique perspective view. In fact, when I say “in mind”, it’s not completely true, as Mike explained us that he had to recover the initial data for ARM1 (layout and paper written specification), back-up on a cartridge, going to University of Cambridge to find a reader, and that he had to manipulate these data quite a bit before being able to exploit it…

I realize that that not so easy to give you the perfect feedback about this presentation. What is missing is the touch of humour that only a British man can give you. As you can see with the syntax in this blog, that’s not the case with me!

By Eric Esteve from IPnest

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High Frequency Analysis of IC Layouts

High Frequency Analysis of IC Layouts
by Daniel Payne on 10-03-2012 at 12:26 pm
Categories: EDA, Siemens EDA

IC designers of passive devices often use empirical approaches to perform High Frequency Analysis (HFA), however there is at least one new approach being offered by Mentor Graphics using a tool flow of:

A recent White Paper was written by Georgios Manetas, Ph.D, Developer and Christen Decoin, Program Manager. I’ll give you an overview from what I read.

Empirical Approach
You could first design multiple silicon test structures for HF devices, create a compact model with TCAD tools and then calibrate the models. Some reasons that make the empirical approach less appealing:

  • Long development time for TCAD models
  • Measurement-based design takes too much time
  • Small changes to the passive device design require new models
  • Parasitic and neighboring device interactions are not accounted for
  • It’s difficult to perform design explorations

Mentor’s Approach
In the opening paragraph I listed all of the Mentor tools used to perform HFA of passives, and here are how the tools would be used:

  • Inductor devices are automatically recognized in the IC layout with either Calibre nmLVS-H or Calibre xRC.
  • Electro-Magnetic (EM) simulation with Calibre xACT-3D, producing S-parameters which are frequency dependent.

Accuracy versus Reference
New approaches must be compared against a reference, so the inductor layout from Figure 1 was used and the two approaches compared. The Mentor S-parameters are within 5% of the reference (TCAD-based) L values, and within 10% of Q values:

Benefits of New Approach
So the accuracy of the new approach looks acceptable, other benefits include:

  • Scalable tool flow, about 10X capacity and performance improvement over TCAD tools
  • Enables device exploration, quickly
  • Tools integrated with full-custom layout editors
  • Analyze with black-boxing to exclude areas
  • Extract and analyze in hours, not days
  • Characterize both HF components and the IC interconnect
  • At validation stage use highest accuracy with good turn around time
  • For design exploration use good accuracy and fast turn around time

Summary
HF designers now have another choice besides a traditional TCAD approach by using Mentor tools. The complete white paper can be found here.

Further Reading

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Linley Tech Processor Conference 2012

Linley Tech Processor Conference 2012
by Daniel Nenni on 10-03-2012 at 7:46 am
Categories: Events, IP
1 Comment


Learn everything you need to know about processors for enterprise- and carrier-communications systems. We have added more Speakers and industry experts and expanded the two-day conference program with 25 % more sessions.

We will be featuring presentations on the newest processors with multiple cores, programmable data planes, and flexible architectures. Additional topics include security and high-performance memories for networking.

Attendees have the opportunity to meet with industry leaders, The Linley Group analysts, and a not to be missed networking reception with over 20 Sponsor Exhibits on Wednesday, October 10 at 5:00 – 6:30 PM. Enjoy the open bar and great food as you relax and compare notes with your peers.

The Linley Group provides independent technology analysis and strategic consulting in semiconductors for a broad range of applications including networking, communications, mobile, and wireless.

We cover emerging areas such as mobile application processors, 3G/4G baseband processors, mobile connectivity chips, Ethernet switch chips and 10GbE PHYs, 10GbE NICs and controllers, high-speed interconnects, embedded processors, security processors, FPGAs for communications, broadband chips, and more. For those seeking quantitative data, we offer market forecast and market share reports for both wired and wireless communications semiconductor markets.

We are the publisher of MicroprocessorReport, the industry’s leading technical newsletter for unbiased, in-depth analysis of high-performance processor technology.

Our analyst team possesses the unique combination of technical expertise and specific market knowledge to help you successfully navigate the complexities of these markets. With broad backgrounds in product design, marketing, management, and industry analysis, we deliver informed, real-world perspectives to your issues.

We provide in-depth technology analysis reports, interactive conferences, and strategic consulting services tailored to the individual client. We help clients understand the market for these devices, vendor strategies, key differentiators, technology trends, and how to select the right device for a specific application. We deliver the crucial information necessary to make intelligent business decisions.

Meet our Analysts

On October 10th and 11th, 2012, The Linley Group will host the Sixth Annual Linley Tech Processor Conference at the DoubleTree Hotel, in San Jose, CA.

» Events | Day One | Day Two | Register

On-line registration for pre-qualified attendees is free if registration forms are received by 6:00 PM PDT on October 4, 2012. Registration for non-qualified attendees is $795 if received by that date. Registration received after October 4 or at the door, will be $195 for qualified attendees and $995 for non-qualified.

Pre-approved attendees from OEMs and ODMs, carriers and service providers, the press, and financial services companies can attend at no charge!
October 10: Conference 9:00 AM – 5:00 PM
October 11: Conference 9:00 AM – 4:30 PM

Featured Keynote Speakers:

Wednesday, October 10 – Linley Gwennap, Principal Analyst for The Linley Group and the industry’s premier expert on the microprocessor technology and markets.

Thursday, October 11 – Andy Bechtolsheim, Founder, Chief Development Officer and Chairman, Arista Networks.

Here is a list of some of the outstanding presenters:

  • Overview of the market and technology trends affecting processors for networking Linley Gwennap, The Linley Group
  • A View from the Cloud: Architecting World’s First 64-Bit ARM Processor Gaurav Singh, Vice President of Engineering and Product Development, AppliedMicro
  • Designing Efficient Processor Cores for the Multicore Networking Market Shubu Mukherjee, Distinguished Engineer, Cavium
  • Break – Sponsored by Freescale (10:30am-10:50am)
  • A Future Coherent Interconnect Technology to Handle Exponential Data-Flow Growth Ian Forsyth, Product Manager, ARM
  • A Next-Generation Multicore SoC Architecture for Tomorrow’s Communications Networks David Sonnier, Technical Fellow and Chief Product Architect, Networking Solutions Group, LSI
  • High-Performance Memories for Packet Processing: Solutions and Outlook Chris Johnson, DRAM Applications Engineering Manager, Micron
  • Networking Memory from Now to 1Tb David Chapman, VP of Marketing & Applications Engineering, GSI Technology
  • A High-Performance, Power-Efficient Memory for Networking Applications Michael J Miller, VP of Technology Innovation and System Applications, MoSys
  • Silicon Convergence: The Future of SoC FPGAs Ty Garibay, Vice President of Engineering, Embedded Processing, Altera
  • A Novel Approach to Scaling Multicore Based Architectures Shreyas Shah, System Architect, Xilinx
  • The Art and Science of Software and Services for Multi-core Processors Imran Badr, Head of Software Engineering, Networking & Communications Division, Cavium
  • Solutions for Software-Defined Networking and Network Virtualization Srinivasa Addepalli, Fellow and Chief Software Architect, Freescale
  • Maximizing Performance and Power Efficiency in Multicore Systems Steve Cox, Vice President of Business Development, Target Compiler Technologies
  • Multiprocessor Cores For Enabling Scalable and Performance-Efficient SoCs Del Rodillas, Director, Networks Solutions, MIPS Technologies and Rao Gattupalli, Principal System Architect for Networking and Communications, MIPS Technologies
  • A Latency-Tolerant CPU Architecture Paul Evans, Business Development Manager, Imagination Technologies and Jim Whittaker, Processor Architect and General Manager, Imagination Technologies
  • A New Processor Family to Enable Heterogeneous, Multiprocessor SoCs Yankin Tanurhan, Ph.D., Vice President of R&D, Processor Cores, IP Subsystems and NVM IP Solutions, Synopsys
  • The Protocol-Processing Dataplane: Extensible Multiprocessors in Networking, Wireless Stacks, and Storage Chris Rowen, CTO and Founder, Tensilica
  • Moore’s Law and Networking Andy Bechtolsheim, Founder, Chief Development Officer and Chairman, Arista Networks
  • Embedded Security and Cryptographic Algorithms, Protocols, and Solutions Bart Stevens, Director of Product Management, Embedded Security Solutions, AuthenTec Q&A with AuthenTec
  • Security from Client to the Cloud—An Architectural Approach for the Infrastructure Praveen Mosur, Principal Engineer, Intel
  • Break Sponsored by LSI (10:40am-11:00am)
  • Security Beyond Data Communications: Deploying System Trust in Embedded Applications Christine Severns, Distinguished Engineer, Chief Security Architect, LSI
  • Processing Demands in Next Generation Networks Eliot Rosen, Product Line Director, Processors and Wireless Infrastructure Group, Broadcom
  • The Case for Compute Offload Using a Manycore Processor Bob Doud, Director of Processor Strategy, Tilera
  • A Flow-Processing Architecture for 100G Applications Daniel Proch, Director of Product Management, Netronome
  • A C-Programmable 400Gbps NPU With Layer 2-7 Features Guy Koren, VP Technology and CTO, EZchip
  • Break Sponsored by Freescale (2:35pm – 2:55pm) Leveraging a Software-Controlled Data Path for Next-Gen Multiservice Routers Altaf Hussain, Senior Product Manager, Freescale
  • A Next-Generation Home Access Point and Router Pravin Bathija, Product Marketing Manager, Processor Business Unit, AppliedMicro

To keep informed about this and other upcoming events, subscribe to Linley Wire, our free email newsletter.

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GLOBALFOUNDRIES and ARM!

GLOBALFOUNDRIES and ARM!
by Daniel Nenni on 10-02-2012 at 8:30 pm
Categories: Arm, Foundries, GlobalFoundries, IP


Clearly the key to success in the foundry business is partnerships. Easy to say, harder to do, here is an excellent example of one that works: GLOBALFOUNDRIES and ARM announced in August 2012 a multi-year agreement to jointly deliver optimized system-on-chip (SoC) solutions for ARM® processor designs on GLOBALFOUNDRIES’ 20-nanometer (nm) and 14XM FinFET process technologies.

For another example check the latest entry on the Foundry Files blog site byDr John Heinlein of ARM:

“Layer Cakes” and Mobile Devices – Yes, There’s a Connection
There’s no denying the pervasiveness of mobile devices and mobile communications technologies. These applications are obviously changing how we communicate and share information, but also increasingly how we do business. And consumers keep expecting more from their mobile devices. Today, the performance and capability in high-end smartphones and certainly tablet computers are getting on a par with notebook computers. Consumers who previously didn’t know or care about technical specifications are being barraged with milliwatts, gigahertz, and nanometers. Form factors of devices are becoming more and more critical to differentiating a device, where new devices are measured in millimeters and grams compared to prior generations……

ARM hands down has the best social media presence in our industry and SemiWiki has learned a lot from them. ARM also has one of the best, if not THE best, technical conferences in the semiconductor ecosystem:

ARM TechCon is the most comprehensive annual event for hardware and software engineers. This event brings together ARM architecture experts and the largest contingency of ARM Connected Community Partners under one roof. Learn, connect and collaborate with some of the greatest ARM design experts in the industry.

To learn more about ARM and GLOBALFOUNDRIES collaboration and understand GLOBALFOUNDRIES added value for your next design come meet them on October 30th at the 2012 ARM TechCon (Santa Clara Convention Center):

ARM Expo (Day 1):

Exhibit Floor, Booth 33

Sponsored sessions (Day 1):

Silicon Validation of GLOBALFOUNDRIES-Cadence Digital Design Flow in 28 nm Using ARM Physical IP.
Speaker: Steven Chan
10:30-11:20am, Room 207 – (session info)

The Era of Extreme Mobility – The FINflection Point.
Speakers: Bruce Kleinman, Subramani Kengeri, Srinivas Nori,Dipesh Patel (ARM)
5:00-6:00pm, room 212 – (session info)
—

To register to attend the 2012 ARM TechCon Silicon Valley, click here

To schedule your sessions during the 2012 ARM TechCon Silicon Valley, click here

I hope to see you there. Since I’m an internationally recognized industry blogger I get in for free! w00t!

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ReRAM/CBRAM at the 2012 IEDM Conference

ReRAM/CBRAM at the 2012 IEDM Conference
by Ed McKernan on 10-02-2012 at 8:10 pm
Categories: Events, IP


Time flies! IEDM time is coming up again (this year on the left coast) and the conference program is now on-line. Lots of interest to the ReRAM/CBRAM community. While some trends are emerging (Hafnium Oxide appears to be the material of choice) there are still plenty of other more contentious issues. ReRAM/CBRAM has reached the Reliability and Modelling sessions and is sure to feature in a Plenary talk and the Tuesday panel session. Christie Marrian, ReRAM-Forum, Moderator has some more thoughts and a handy guide for the panel session. Check out Christies Blog at ReRAM-Forum.com.

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Dilbert Does Social Media!

Dilbert Does Social Media!
by Daniel Nenni on 10-02-2012 at 7:15 pm
Categories: General
8 Comments

Dilbert has always been a favorite comic of mine because it is based on truth and there is no better humor than truth, especially at work. According to Wikipedia; Scott Adams and Dilbert came to national prominence through the downsizing period in 1990s America. A former worker in various roles at big businesses, he became a full-time cartoonist in 1995. Adams writes in a satirical, often sarcastic way about the social and mental landscape of white-collar workers in modern corporations and other large enterprises.


Scott really nailed it on this one. According to Wikipedia; Social media employ web- and mobile-based technologies to support interactive dialogue and “introduce substantial and pervasive changes to communication between organizations, communities, and individuals.” The problem is that social media is not an art or a science but an interesting combination of both.


Done correctly, social media is the most powerful form of communication our industry will ever experience. Done incorrectly, social media is the biggest waste of bandwidth our industry will ever experience. It’s time we take social media seriously. It’s time for us to harness the power of the fabless semiconductor ecosystem and start communicating using the devices we have enabled.

Done correctly, social media enables original content and dialog from trusted sources who share experiences, observations, and opinions. Done incorrectly, social media enables content based on rumors, innuendos, and flat out lies from people who Google around and quote “anonymous” sources for a living.

Social media analytics is the science behind the art. If you are not measuring your social media activities you are not doing your social media job, simple as that. According to LinkedIn there are about 500,000 people in the semiconductor ecosystem so SemiWiki’s 380,000+ unique visitors is a significant number. Unfortunately 380,000+ people will not read every blog, wiki, forum post, or banner. Even if they did, what would that really prove?

Seriously, social media is a quality versus quantity measurement. Looking at how many people read your post is one data point, knowing who those people are is another, and seeing what action those people take is probably the most important. The ratio between the three is the measurement you really want and here is a simple example:

Free whitepaper on RF CMOS Design at 60 GHz
Hello,

At this year’s Design Automation Conference in San Francisco, Helic and TSMC co-organized a workshop on “CMOS Design at 60 GHz and Beyond: Capabilities and Challenges”, with speakers from Silicon Image, TSMC, Helic, KU Leuven, Integrand Software, and Presto Engineering. A white paper on the workshop can be found here:

http://www.helic.com/veloceraptorx/whitepaper_60GHz

Hope you enjoy.

This was posted in the SemiWiki AMS Design forum by Dr. Sotiris Bantas, CTO of Helic (I added the LinkedIn share button java code). So far more than 700 people have viewed this, more than 100 people have shared this, and more than 80 people have registered with their contact information and downloaded the white paper, simple as that, social media done correctly.

A white paper or webinar blog, the mainstay of SemiWiki, is a better example. One of the SemiWiki bloggers with 25+ years of experience in the semiconductor ecosystem will download the white paper or attend the webinar and blog it. If you read a 500 word summary and click over to download or view something that is what you would call a qualified click, the ultimate social media ROI measurement.

One thing I have noticed during my 28 year career in Silicon Valley is that today people don’t get out as much professionally. Seriously, it is very hard to get people out of their cubicles due to the increasingly fast pace of the semiconductor ecosystem. On the other hand people are much more connected through their mobile devices which makes digital and social media all the more important if done correctly so don’t forget to download the SemiWiki app for Android or Apple IOS.

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Dimensions of Electronic Design Seminars

Dimensions of Electronic Design Seminars
by Paul McLellan on 10-02-2012 at 6:37 pm
Categories: Ansys, Inc., EDA

ANSYS and Apache are putting on a new series of seminars about designing future electronic systems. These are only getting more complex, of course, cramming more and more functionality into smaller portable devices with good battery life (and not getting too hot), integrating multiple antennas into a single platform, and TSV-based 2.5D and 3D designs.

If you attend the seminar you will get technology updates on ANSYS HFSS (the industry standard for 3D full-wave electromagnetic field simulation), Apache RedHawk, and ANSYS SIwave (for complete channel analysis of PCB and IC packages). You can see from this list that more and more the Apache and ANSYS products are being used together for complex analysis. The seminar will also discuss future integration of ANSYS and Apache products that will revolutionize Chip-Package-Sytstem (CPS) design. Each seminar also will have real designers sharing their experience as to how to meet all the Ps for their design: power, performance, price.

The seminars are free to qualified attendeed. However, seating is limited so you must sign up in advance. The registration page is here.

There are four seminars currently scheduled:

  • Thursday October 11th at Sheraton Framingham MA. Detailed agenda.
  • Thursday October 18th at Hyatt Regency Santa Clara CA. Detailed agenda.
  • Wednesday October 24th at Manhattan Beach Marriott CA. Detailed agenda.
  • Thursday November 1st at Hyatt Regency Austin TX. Detailed agenda.

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Cooley on Synopsys-EVE

Cooley on Synopsys-EVE
by Paul McLellan on 10-02-2012 at 7:56 am
Categories: EDA, Synopsys
9 Comments

John Cooley has an interesting “scoop” on the Synopsys-EVE acquisition. The acquisition itself is not a surprise, it is the one big hole in Synopsys’s product line and EVE is the perfect plug to fill it. It was also about the only thing Cadence has (apart from PCB) that Synopsys does not.

The interesting thing is that John noticed it via a filing in San Jose district court where a document said that Synopsys entered into an agreement to acquire EVE on Septemeber 27th. Even before the acquisition is even announced (when, presumably, Synopsys would inherit the EVE-Mentor legal stuff) Synopsys seems to be suing Mentor to get a ruling that Mentor doesn’t have a leg to stand on.

What I don’t understand is how, under full-disclosure rules, it is acceptable for Synopsys to tell the court without telling analysts and, indeed, everyone else by a press release. Right now I’m in China and for some reason the great firewall won’t let me access the Synopsys website (all that subversive simulation technology or something) but I can access the EVE website and there is nothing there about any acquisition. Synopsys is a $1.75B company and EVE is a $60M-ish company so perhaps it is regarded as completely non-material but I’ve never seen anything like it where via one obscure channel the company is aannouncing the acquisition while via the normal channel for announcing these things there is silence. I wonder what would happen if someone formally asked the company about it: “we never comment on takeover rumors” is the usual response of course.

Presumably more will become clear in the next few days, perhaps even tomorrow. We shall see.

Another interesting question, mainly of prurient interest, is who leaked it to John. I mean I can’t believe he is a daily reader of San Jose court documents.

More details on deepchip here.