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Semiconductor Expert Forum

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Bats about DAC!

Bats about DAC!
by SStalnaker on 05-23-2013 at 8:05 pm
Categories: EDA, Siemens EDA

DAC 2013 is closing in fast now…and if you haven’t made your plans for what you want to see and do, you’d better get going! Of course, I’m happy to help you out with a few suggestions…starting with that most important objective—conference swag. Stop by the Mentor Graphics booth (#2046, for those of you who actually look at your floor maps) any time Monday through Wednesday to pick up your plush Congress Bridge bat. And if you get the chance, go out one night and watch the real thing (take your camera!).

For those who like a bit of anticipation, we also have daily drawings. Prizes this year include an Apple iPad[SUP]®[/SUP]Mini, a Nintendo Wii U™, and a GoPro[SUP]®[/SUP]camera. You get an entry for every Mentor suite session you attend, and drawings will be held every day at our Happy Hour open bar, which starts at 4:00 pm. You don’t have to be present to win, but you must pick up your prize in person before the close of DAC.

If a lively bit of discussion is your thing, Mentor is participating in or hosting a number of panels at DAC. Join us for any or all. No advance registration is required.

Achieving IC Reliability in High Growth Markets
Monday, June 3, 3:00-4:00 (Mentor Booth #2046)

Will Data Explosion Blow Up the Design Flow?
Monday, June 3, 3:15-4:00 (DAC Pavilion Panel, Booth #509)

Advanced Node Reliability: Are We in Trouble?
Tuesday, June 4, 10:30-12:00 (DAC Technical Panel, Room 16AB) requires full conference access

Marrying More than Moore
Tuesday, June 4, 3:00-4:00 (Mentor Booth #2046)

No Fear of FinFET
Wednesday, June 5, 3:00-4:00 (Mentor Booth #2046)

It’s also worth noting that the Mentor Booth panels are followed immediately by the Mentor Happy Hour—great chance to mingle with like minds, while enjoying an adult beverage!

As for those suite sessions—as usual, we’ll be hosting a variety of presentations at the Mentor booth. Below are just a few that might appeal to the Design to Silicon crowd, but you can check out the full list any time. Registration is required to attend a suite session—click on the session title to get to our registration page.

Reliability Checks for Multiple Markets(Presented in Mandarin)
Monday, June 3, 10:00-11:00, Mentor booth #2046
你說中文嗎? 你说中文吗? Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. In this session, presented in Mandarin, Mentor Graphics and SMIC discuss reliability checking with Calibre PERC. Want to hear it in English? Sign up for one of the Comprehensive Circuit Reliability with Calibre PERC sessions (Monday, 2:00 or Wednesday, 10:00) in the Mentor booth.

Best Practices for 20nm Design
Monday, June 3, 2:00-3:00, Mentor booth #2046
If you’re planning or contemplating a move to 20nm, you need to be in the seats for this session. TSMC and Mentor present best practices learned from their experience helping leading-edge customers with the transition to 20nm. This vital knowledge will help you smoothly tapeout your designs for TSMC’s advanced processes.

Advancing Circuit Reliability at TowerJazz with Calibre PERC Rule Decks
Tuesday, June 4, 2:00-3:00, Mentor booth #2046
Intended for advanced Calibre users, this presentation demonstrates how TowerJazz uses Calibre PERC rule decks and the Calibre PERC product’s unique ability to combine schematic (netlist) and physical layout information to perform circuit reliability verification during signoff. ONE TIME ONLY, LIMITED SEATING.

Preparing for Pervasive Photonics
Tuesday, June 4, 2:00-3:00, Mentor booth #2046
Silicon photonics is coming—are you ready? This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that SP will open up, and new challenges it will present to IC designers.

Of course, we won’t just be hanging out at the Mentor booth the whole time. Calibre experts will be speaking at our partners’ booths as well. We have a full list of partner activities, but here’s one technical presentation you won’t want to miss:

Identifying Critical Design Features from Silicon Results
Tuesday, June 4, 10:00-11:00, GLOBALFOUNDRIES Booth #1314
Ken Amstutz (Senior Application Engineer) will be talking about the collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design- and process-induced defects. LIMITED SEATING – REGISTRATION REQUIRED

For a full round-up of Mentor activities at DAC, and to register for any of our suite sessions in advance, you can check us out at Mentor@DAC 2013. See you in Austin!!

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Network-on-Chip is the backbone of Application Processor and LTE Modem

Network-on-Chip is the backbone of Application Processor and LTE Modem
by Eric Esteve on 05-23-2013 at 9:38 am
Categories: Arteris, IP

I have mentioned NoC adoption explosion during the last two years, illustrated by the huge revenue growth of Arteris. This trend is now confirmed in the fastest moving segments, the Application Processors (AP) and LTE Modem for mobile applications. In fact, Arteris FlexNoC has been integrated in the majority of AP and LTE Modem chips being shipped in 2012 and shipping in 2013. What is the common and key feature for these chips?

Each of these is shipping by dozen of millions, all of them are extremely complex, counting 100 IP or more, and the Time To Market (TTM) is dramatically important: if a chip maker miss the release to production by only one months, several dozen if not hundred $ millions of chip sales just vanishes… and will never be catch-up, because OEM integrating these IC like Apple, Samsung or HTC have to release a new product generation almost every 6 months. If you take a look at the business won by Arteris since 2008, you will name most of the major semiconductor companies (even if you are not supposed to know the name of “Unannounced Customer”, just think about “Major”…).

If you come back to one of my very first post about Network on Chip, you remember that one of the most important NoC advantage is to avoid routing congestion on large SoC, thus accelerating TTM as the back-end cycles (Place and Route/post routing simulation/modification) are extremely time consuming. But we know that for IC like AP and LTE Modem, the key sales message will be about Performance, measured in term of main CPU Frequency, and Low Power, as these will be the most visible feature for the end user: can I use my smartphone right after opening it? Do I need to plug it every two hours or could I use it for days before charging? Arteris’ FlexNoC is also addressing these two very important requirements that every chip maker has… or that the company should have, in order to be successful!

It’s very interesting to see that the very fast growing chip makers or ASIC companies are also adopting the NoC, and the reasons why they adopt Arteris’ FlexNoC: high frequency, low gate count, lower power, higher flexibility or Quality of Service (QoS) are the most frequently mentioned advantages.

Fuzhou Rockchip Electronics Co. Ltd.
“Arteris FlexNoC interconnect IP enables us to exceed our design frequency and power requirements while giving us more flexibility than possible using older interconnect technologies, like buses and crossbars,” said Li Shiqin, IC Design Manager at Rockchip.

MegaChips Corporation
“From our experience with Arteris’ NoC technology over the years, we knew that Arteris FlexNoC IP was the fastest interconnect fabric for SoCs with multiple initiator and target IP blocks. However, we were surprised that FlexNoC could continue to run at fast design frequencies with a significantly lower gate count and less power consumption than alternative bus fabrics,” said Gen Sasaki, General Manager of Division No.2, MegaChips Corporation.

Open-Silicon, Inc.
“Arteris’ network-on-chip interconnect IP made timing closure much easier and allowed us to implement the QoS management required for the design’s high-performance I/O and sophisticated hardware acceleration engines. In addition, we were able to close timing in a fraction of the schedule needed previously for designs using older crossbar-based architectures,” said Colin Baldwin, senior director of marketing, Open-Silicon

When you see such a customer list, you understand why the company is claiming that FlexNoC is integrated into about 60% of the Application Processor and LTE Modem IC. When you know the associated shipments in smartphones and media tablet applications, you can guess that Arteris royalty revenues will sky rocket in 2013 and after!

To learn a lot more about NoC and Arteris products, just go here.

By Eric Esteve from IPNEST

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Do You Need to Worry About Soft Errors?

Do You Need to Worry About Soft Errors?
by Paul McLellan on 05-22-2013 at 6:51 pm
Categories: EDA, IROC Technologies

As we get down to smaller and smaller process nodes, the problem of soft errors becomes increasingly important. These soft errors are caused by neutrons from cosmic rays, alpha particles from materials used in manufacture and other sources. For chips that go into systems with high reliability this is not something that can be ignored. Everyone in the design and supply chain has a part to play:

  • foundries and packaging for material choice and characterization
  • library designers, memory and storage elements
  • SoC designers, characterize reliability of design and improve if required
  • System architects to define the reliability needed


Next week, Adrian Evans of IROCtech will present a short webinar on the topic. The agenda is:

  • Soft Error Rate (SER) trends
  • What are the impacts of SER?
  • What can be done about it?
  • Customer case study
  • iROC services and products
  • Q&A

The webinar is on Thursday at 11.30am Pacific Time (although I believe Adrian will be presenting from France). I will be the moderator.

To register go here.

IROC is the standard for soft error analysis and prevention. With the introduction of submicron technologies in the semiconductor industry, chips are becoming more vulnerable to radiation induced upsets. IROC Technologies provides chip designers with soft error analysis software, services and expert advisors to improve a chip’s reliability and quality. Exposure of silicon to radiation will happen throughout the lifetime of any IC or device. This vulnerability will grow as development moves to smaller and smaller geometries. IROC proved that the soft errors that cause expensive recalls, time-to-volume slow-down, and product problems in the field can be significantly reduced. The mission of the company’s soft error prevention software and expert advisors is to allow users to increase reliability and quality while significantly lowering the risk of radiation-induced upsets, throughout the lifetime of products under development.

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IC Place and Route Perspective from Users at DAC

IC Place and Route Perspective from Users at DAC
by Daniel Payne on 05-22-2013 at 11:44 am
Categories: EDA, Siemens EDA

One of the most useful ways to learn about an EDA tool is to talk with other users that have experience with that tool. IC Place and Route tools are complex and yet necessary to implement every SoC designed today, so at DAC in just two weeks you have a chance to hear first-hand from several P&R tool users. To get a better idea about these P&R users and their IC design challenges I talked with Sudhakar Jilla of Mentor Graphics by phone.


Sudhakar Jilla, Mentor Graphics
Continue reading “IC Place and Route Perspective from Users at DAC”

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Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic

Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic
by Daniel Payne on 05-22-2013 at 10:25 am
Categories: Ansys, Inc., EDA

Nvidia designs some of the most powerful graphics chips and systems in the world, so I’m always eager to learn more about their IC design methodology. This week I’ve had the chance to talk with Ting Ku, Director of Engineering at Nvidia about his DAC talkin the Apache booth in exactly two weeks from today. Registration is required for this presentation.


Ting Ku, Nvidia

Continue reading “Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic”

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The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows

The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows
by Daniel Nenni on 05-22-2013 at 10:00 am
Categories: Cadence, Cliosoft, EDA

As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing revision control, design management and multi-site team collaboration for Aglient Technologies’ Advanced Design System (ADS) Software and Mentor Graphics’ Pyxis flow. SOS is now seamlessly integrated into all major analog, RF and custom IC design flows:

  • Agilent ADS
  • Cadence Virtuoso®
  • Mentor Pyxis
  • Synopsys Laker™
  • Synopsys Custom Designer

In booth #2125 ClioSoft is replacing its popular poker game with slot car racing. As much as I like playing poker, slot car racing brings me back to my childhood so I’m looking forward to it. Maybe next year I can get them to install a massive HO scale train set? My brothers and I spent hours and hours playing with model trains.

Here is what customers are saying about Cliosoft products on SemiWiki:
[LIST=1]

Supporting the Customer Is Everyone’s Job

Cliosoft CEO on Design Collaboration Challenges!

Agilent ADS Integrated with ClioSoft

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Transistor-Level Update from Cadence at DAC

Transistor-Level Update from Cadence at DAC
by Daniel Payne on 05-20-2013 at 7:47 pm
Categories: Cadence, EDA

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.

Here’s what I would recommend attending at Cadence in Booth #2214: Continue reading “Transistor-Level Update from Cadence at DAC”

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Samsung’s Life of Pi @ Apache @ DAC

Samsung’s Life of Pi @ Apache @ DAC
by Paul McLellan on 05-20-2013 at 4:51 pm
Categories: Ansys, Inc., EDA

Last week I talked to Eileen You of Samsung-SSI to get a preview on what they will be talking about at Apache’s customer theater at DAC. Their presentation is titledThe Life of PI: SoC Power Integrity from Early Estimation to Design Sign-off. The ‘PI’ stands for Power Integrity.

Samsung-SSI’s operations are 5 years old and have grown from 1 person to 100 and have gone through several generations of technology. Some designs are 28nm and other are currently below.

Apache tools are used to generate scenarios for power analysis and integrity. Power analysis is dependent on vectors for realistic scenarios but that is a really hard challenge they find. They are trying to expand up to the RTL level since there is too little gain from doing analysis post-synthesis since the design is hard to change.

Primarily Samsung are using RedHawk, CPM and Sentinel. Redhawk for general power analysis. For package and board they use Sentinel. Packages need to be analyzed in the frequency domain and in the time domain.

The future challenges they see are mostly big picture stuff: power grid design, power regulators, keeping costs under control with the right metal stack, and, of course, the big one that everyone faces that power density is increasing. Rocket nozzles anyone? As designs get bigger and processes have less margin, obviously higher accuracy, higher capacity. Plus getting good power vectors so that the analysis done is realistic. It is easy to waste a lot of time doing very accurate analysis with bad vectors.

The abstract of Samsung-SSI’s presentation: The life of Power Integrity (PI) analysis starts at the product infancy stage. Early analysis involves resource allocation at the system level, such as the VRM, board, and package, and at the chip level, in terms of power grid structure, power scenario analysis, and the amount and placement of intentional decoupling capacitance (DECAP). This is done through systematic PI modeling and simulation. As the design matures, the power integrity engineer gets more information on the system and on the die. There are many phases of progressive iterations to evaluate design tradeoffs. Power integrity engineers work closely with board, package, and chip design teams to achieve PI closure. At the design tape out stage, the power integrity team is responsible for signing off static and dynamic IR drop and EM to verify that multi-million gates SoC chips meet stringent power supply noise budget. We investigated the impact of board, package, package embedded with DECAP, power grid, circuit switching activity, as well as on-die DECAP and demonstrated good correlation between early estimation and the final analysis with detailed chip and package models.

To register for this or other customer presentations at the Apache booth at DAC go here.

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Better, Faster, Cheaper: Evaluating EDA tools

Better, Faster, Cheaper: Evaluating EDA tools
by Randy Smith on 05-20-2013 at 3:30 pm
Categories: General

With DAC approaching, it is a good time for both EDA companies and their customers to take a deeper look at the evaluation process of EDA tools, and how EDA companies position their tools. I hope this is useful for customers and vendors alike.

When it comes to positioning EDA tools in the marketplace there are really only three meaningful measurement scales. Products will primarily be categorized as: (1) Better; (2) Faster; or (3) Cheaper. Of course, Faster could be used as better performance and Cheaper could be viewed as better price. However, I break it down this way because, on the equivalent of the Mazlow Scale of EDA, a Better product is usually more highly valued (e.g., optimization) than a Faster product (e.g., simulation technology treadmill) or a Cheaper one. While this method is taught in one way or another at most business schools, it is relentlessly drummed into the heads of the executives and marketers at all companies mentored by EDA icon, Jim Hogan (who says he actually borrowed it from Isadore Katz). So, for now, I will refer to this as the Hogan Scale.

What makes a product better? Generally we look at two broad categories – quality of result (QoR) and ease-of-use. The method to measure QoR will vary based on the product category. For example, you might measure QoR for a IC place and route product by result chip performance, power, and area (PPA). For a circuit simulator QoR may be primarily measured on accuracy or debugging support. Each customer needs to list and rank the criteria that matters to them. Do not include vendor-touted features unless they matter to you over the time period of the license you are considering buying.

Most benchmarks focus on QoR, leaving ease-of-use as a part of the Better measurement that is often undervalued. However, sometimes ease-of-use is measured in total clock time (set up time and difficulty; and run time). If a tool only gives good results when run by the vendor’s application engineers then you have a potential problem for several reasons: (1) you will always be dependent on support from the vendor just to get good results from the tool; (2) you may end up competing with other companies over who gets the better support from vendor; (3) if you cannot get the support you need, or perhaps cannot afford it, the tool will go underutilized; and (4) your development team may not be able to express their expertise since they cannot adequately drive the tool. To summarize, if ease-of-use is low either you won’t see the QoR you saw in the benchmark when you use the tool yourself, or you will need to rely on the vendors AEs which may be quite expensive. Perhaps more disturbing, the availability of the vendors AEs is not typically under the customer’s control.

Measuring Faster is pretty straight forward and simply requires that you give the tools you are measuring a similar amount of resources. You may need to be a bit flexible with that at times. If one vendor supports parallel processing and another does not you simply need to consider what speed you require or how much more you are willing to pay for the higher speed. Faster will often lead to better. In the classic trade-off, if you can run simulation fast, then you can do more verification by running more simulations to get better quality results from verification.

Cheaper is often a pejorative term. In this context we simply mean less expensive. If two tools are essentially similar in QoR, ease-of-use, and speed, then price will make the difference. Where there are clear differences between the tools customers should consider if saving on license cost is actually worth it. EDA tools should be a multiplier of value for customers, not a necessary evil or cost. Good engineers will produce noticeably better results with good tools than they will with bad ones.

Finally, I have been asked by small companies and other bloggers how small EDA companies can, or should, compete with the major EDA vendors. It starts by knowing where you are on the Hogan Scale. If your Better is enough, then promote that. If not, are you Faster? Cheaper simply never works for a start-up. Competing on price with the big vendors is a bad place to be.

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