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Can Samsung Deliver As Promised?

Can Samsung Deliver As Promised?
by Daniel Nenni on 03-24-2013 at 8:01 pm
Categories: Foundries

Samsung’s aggressive marketing is starting to hit the fabless semiconductor ecosystem so we had all better be prepared. Samsung’s 2012 marketing budget exceeded $400M which probably beats the marketing budget of the entire fabless ecosystem! The question is, will the fabless semiconductor industry be easily swayed by Samsung’s clever marketing? Let’s take a look at their recent mailer and see:

Samsung is fueling the innovations that are changing the way we connect, interact, and benefit from technology. Our low-power, high-performance components and advanced process manufacturing are the foundation for your next leap in mobile products and the infrastructure that connects them. Connect with Samsung and stay abreast of our latest solutions.

This email talked about 14nm and getting ready for FinFET design. According to what I hear in Silicon Valley, Samsung is claiming to be far ahead of the competition and that is confirmed here:

GET READY TO DESIGN 14nm PROCESS IS HERE!

The foundry business is all about setting customer expectations and meeting them. Let’s take a look back at 28nm. According to an EETimes article dated 6/6/2011:

South Korea’s Samsung Electronics Co. Ltd. said Monday (June 6[SUP]th[/SUP]) that its foundry business, Samsung Foundry, has qualified its 28-nm low-power (LP) process with high-k metal gate technology and is ready for production.

Where is the qualified 28nm silicon they speak of almost two years ago? Why does my iPhone5 have a Samsung 32nm based SoC? Why does TSMC have 99.99% 28nm market share? If you want someone to blame for the 28nm shortage how about Samsung? Clearly they did not deliver. Barely a month later (7/12/2011) EETimes reports:

Samsung Electronics Co. Ltd. has said that is foundry chip making business has taped out an ARM processor test-chip intended for manufacture in a 20-nm process with high-K metal-gate technology.

Where is the Samsung 20nm silicon they speak of? I’m waiting for a teardown of the new Galaxy S4 but knowing that the S3 is powered by a 32nm Samsung SoC I highly doubt we will see a Samsung 20nm SoC anytime soon.


Speaking of marketing smoke and mirrors, I was at the Samsung keynote at CES where the Exynos 5 Octa SoC was launched claiming to be the first (8) core SoC. There was a more technical presentation at ISSCC a month later. In reality, the Exynos 5 Octo is (4) off the shelf ARM A15 cores plus (4) off the shelf ARM A7 cores in a Big/Little configuration where only (4) cores can be used at a time. What a mess, they should have named it Octomom!

Meanwhile, back on planet Earth, Apple and Qualcomm license the ARM architecture and create highly integrated custom SoCs tuned for the associated operating system, which is why they have the best performance/battery life ratio on the market today. How long until APPL and QCOM have the ARM 64 bit architecture rolled out? Closer than you think, believe it.

Time will tell but based on previous Samsung marketing materials for 28nm and 20nm, Samsung 14nm may not be as close as it appears. Samsung 28nm test chips were announced June of 2010 and hopefully we will see 28nm production silicon 3 years later. Samsung 20nm test chips were announced July 2011 with silicon expected in 2014? Samsung 14nm test chips were announced in December of 2012 so you do the math. Maybe Q1 2016? If so they are behind the competition, certainly.

Of course that will not stop the Samsung propaganda machine. As they say, the pen is mightier than the sword and $400M buys a whole lot of ink!

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Unlocking the Full Potential of Soft IP

Unlocking the Full Potential of Soft IP
by Daniel Payne on 03-22-2013 at 11:32 am
Categories: EDA, Sonics, TSMC

EDA vendors, IP suppliers and Foundries provide an eco-system for SoC designers to use in getting their new electronic products to market quicker and at a lower cost. An example of this eco-system are three companies (TSMC, Atrenta, Sonics) that teamed up to produce a webinar earlier in March called: Unlocking the Full Potential of Soft IP.


Continue reading “Unlocking the Full Potential of Soft IP”

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A Brief History of Forte Design Systems

A Brief History of Forte Design Systems
by Daniel Nenni on 03-21-2013 at 8:10 pm
Categories: EDA

When Semiwiki readers see the name Forte Design Systems, they may think of the live bagpipers’ performance that closes the yearly Design Automation Conference. Forte has been the sponsor of this moving end to DAC since 2001. Step with me behind the plaid kilts for a good look at this remarkable company headquartered in San Jose, Calif., enabling remarkable designs.

Forte finished 2012 with 22% growth, and boasted that 2012 was the seventh consecutive year of revenue growth. Better yet, it was named the #1 provider of electronic system-level (ESL) synthesis software by Gary Smith EDA. Forte prefers high-level synthesis (HLS) –– a way for hardware engineers to work at a higher level of design abstraction –– to the ESL acronym and, in fact, is credited with defining the market. Sean Dart, CEO, and Brett Cline, vice president of marketing and sales, cite a strong commitment to high-value software and top-notch support for moving into the top slot.

Forte has been around since 2001, not to sponsor the bagpipers but after CynApps and Chronology merged. The name was chosen appropriately enough because it’s a noun that means “good at” or “strength.” Long-time industry observers will remember that Dr. John Sanguinetti started CynApps in 1998 after Chronologic and VCS, the popular Verilog Compiled Simulator, were acquired by Viewlogic in 1994. (Synopsys acquired Viewlogic in 1997 and continues to sell VCS today.)

Dr. Sanguinetti is Forte’s CTO and knew back in the early 1990s that logic verification and logic synthesis were two big EDA problem areas. He took on logic verification at Chronologic, then turned his attention to logic synthesis, knowing that the change in abstraction levels from gates to register transfer level (RTL) would improve design and verification efficiency. That would be enabled by logic synthesis. In 1998, he and two other engineers founded CynApps to create a higher level design environment, along with a synthesis product that would produce RTL code from higher level designs.

Then came the 2001 merger of CynApps and Chronology with synthesis and verification offerings. Chronology was a verification provider, but not as well known or successful as Verisity (now part of Cadence). With a visible presence and good reputation in the synthesis space, CynApps could attract funding. The decision was made to continue to focus on high-level synthesis and use the verification tools to build a high-level synthesis environment with verification at its core. The move to a high-level synthesis business model was soon validated –– Fujitsu, Ricoh and Sony were among the first Forte customers that year.

Asia’s consumer electronics companies were the first to adopt a high-level synthesis methodology ahead of other regions. Japan’s consumer device designs were a natural fit for this kind of software because HLS can implement image-manipulation algorithms into hardware.

Cynthesizer, Forte’s SystemC high-level synthesis, is selected by development teams who want to reduce time-to-market pressures by designing at a higher level of abstraction and require substantial improvements in circuit size and power. In many cases, teams create designs that would be impossible using RTL. United States, Korea and Japan, in particular, are design centers where Cynthesizer is in use for custom processors, and wired and wireless communication devices.

In 2009, Forte acquired Arithmatica to complement its product offerings with a portfolio of intellectual property (IP) and datapath synthesis technology that has been integrated directly into Cynthesizer.

Moving design to a higher level of abstraction has been a tough challenge that Forte solved and its production-quality tools are going mainstream to prove it. Of course, Forte will be at the 50th DAC in Austin, Texas, and is planning already for the return of the bagpipers this year.

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Mixed-Signal SoC verification has integrated solution

Mixed-Signal SoC verification has integrated solution
by Pawan Fangaria on 03-21-2013 at 8:10 pm
Categories: Cadence, EDA

These days when we talk of SoC verification, what comes to our mind immediately is VirtualPlatform. Of course with the increasing size, complexity and different styles of designs, it is very much a need.

However, that is supported by actual verification engines and methodologies which are varying considerable with digital, analog and mixed-signal portions of the design. Gone are the days when we used to embed pre-verified analog block into digital design with identified signals interfacing between them. Conversely, digital blocks were imported into analog centric designs. Today, we have large analog, digital and mixed signal design content, all sitting together in an integrated design and interacting with multiple signals continuously. And almost in all designs, mixed-signal content is inevitable.

Typically, analog components are simulated by Spice and its variants and digital simulation is simplified by discrete data models simulated through Verilog or VHDL simulators. As design complexity has increased along with the need of analog and digital components staying together, various methodologies, languages and tools have emerged for modelling and verifying analog, digital and mixed-signal designs with trade-off between accuracy and performance/capacity.

Verilog-A, Verilog-AMS, VHDL_AMS, SystemVerilog and now SystemC (extended to
SystemC AMS for system level mixed signal modelling) provide tremendous capabilities to model analog and digital content together which can be efficiently simulated by a standard tool having single kernel in optimum time and desired level of accuracy. Cadence provides a suite of tools and techniques applicable in various contexts to solve this challenging problem of verifying complete SoC mixed-signal design. It provides a seamless environment with unified GUI which integrates its simulation engines, design environment and verification methodologies together to provide a unique experience to the user. I came across a white paper of Cadence which describes the verification solution with nice level of details. The white paper can be found at –
http://www.cadence.com/rl/Resources/white_papers/ms_soc_verification_wp.pdf

As an example Virtuoso AMS Designerlinks Virtuoso custom design platform with Incisive verification platform. It supports simulators like Spectre and Spectre RF Circuit Simulators, UltraSim Full Chip simulator, Accelerated Parallel Simulator and Incisive Enterprise Simulator; all integrated together in common GUI and used as per need.

For interface and translation between discrete levels of digital signals and continuous voltage levels of analog signals is done automatically through special connection modules. Common Power Format (CPF) is used with novel techniques to distinguish between a functional error and a false error due to power shut down in a particular digital or analog portion of the circuit (which usually is a case with low power design to save power that advocates to keep power ON only for active circuitry at a time). Again provisions for levels of abstractions from behavioural up to transistor level have been provided.

Just a glimpse of how the digital centric and analog centric methodologies are being unified has been represented as –

To sum it up, while Spice simulators help in verifying individual analog IP blocks, as we move up towards full chip verification of mixed signal SoCs, analog behavioural models embedded with digital languages and the techniques and tools associated with them provide up to 100x speed up in the complete SoC verification.

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Data Management for Designers

Data Management for Designers
by Paul McLellan on 03-21-2013 at 8:05 pm
Categories: Cliosoft, EDA

Back when I was a programmer at VLSI Technology in the mid-1980s, I was responsible for all the data management in the VLSI Design Tools. By responsible for, I mean that I designed the whole system and wrote all the code. Prior to the 5th release of our product, there was no data management, designers simply used filenames and it was up to them to keep track of what they were doing. Of course, as software developers, we had a source-code control system. We actually rolled our own before eventually we switched to ClearCase years later, then almost the standards before the open source alternatives like subversion and git took over.

The challenge with data management for designers is three fold. Firstly, designers are not software engineers and so complex configuration schemes the software people are used to are going to either baffle them or not get used. By complex configuration I’m talking about things like forks and merges. Secondly, designers often live in a graphical environment on their desktop and are not just typing commands into a command line interface. This means that any data management needs to be integrated into the tools so that it doesn’t require the designer to go somewhere different. The third thing is that the files involved are either binary or, even if text, are meaningless to the designer and only mean anything to the software engineers creating the tools. For example, looking for changes in a netlist the way it is represented in a file using a text diff type tool is not useful.

I implemented the standard checkout/checkin procedure, whereby each designer had their own sandbox (I called it a working library) and projects had a controlled library, and then there would usually be several read-only libraries that held things like standard cell data and could not simply be changed and usually formed part of the release of the process node from the foundry (or, in the case of VLSI, our own library development organization). These were integrated into the tools cleanly. If a designer in a layout editor changed a cell, it would automatically be checked out.

It is interesting how many of these basic concepts live on in ClioSoft’s data management. The implementation is more modern, and it has to be integrated into several different layout/schematic environments, not just one. Almost all designs teams are geographically distributed these days so that needs to be cleanly supported. Designs have grown so large, too, that optimizing the use of disk space is important, rather than duplicating every file many times.

But it is still the case that design is very different from software development:

  • Users are working at higher abstraction levels such as libraries and cells and are not necessarily aware of the directories and files that store the data.
  • Design tools create files that contain design data as well as temporary run files that need not be managed. End users do not know which files should be managed and which should not.
  • A design flow has several complex tools sometimes from different vendors. Each tool organizes data files in different ways.
  • A design object such as a schematic or layout is usually made up of multiple files created by the design tool with software-generated names.
  • The size of the data is much larger. There are many more files and several of them are large binary files.
  • Designers often think in terms of design hierarchy that is not apparent when looking at the file system.

The bottom line is that it is not appropriate to use a software-oriented configuration management system for managing design data. It is not integrated with the design tools, it requires designers to know far more than they should about how their data is actually represented on disk and it forces them to learn unfamiliar concepts.

ClioSoft’s data management addresses these concerns. It has a simple model, with the complexity hidden by the ClioSoft software. It is cleanly integrated into all the most popular layout environments (for example, the above picture shows the integration with Cadence’s Virtuoso environment, but it is also integrated with Synopsys Custom Designer and Mentor’s Pyxis). And it understands design representations so that it can show changes in the same graphical environment.

Also Read

Modern Data Management

Cadence ♥ ClioSoft!

A Brief History of ClioSoft

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Simon Segars to be New CEO of ARM

Simon Segars to be New CEO of ARM
by Paul McLellan on 03-20-2013 at 4:15 pm
Categories: Arm, IP

ARM announced today that Warren East, the CEO, would be retiring at the end of June. The new CEO will be Simon Segars, currently President of ARM and the de facto #2 guy. Currently Simon is based in the US and I don’t know if he plans to return to Britain or not. But he will live what will inevitably be a lifestyle that involves crossing the Atlantic a lot, no matter which side he picks.

It is interesting that ARM will have a new CEO this year since their big rival in the microprocessor business, Intel, will also have one. Intel announced that Otellini will be stepping down in May, but they have a search going on for the successor.

I installed the design tools used to design the first ARM processor, inside Acorn Computer. I was there when ARM was spun out of Acorn since VLSI Technology provided all the design tools ARM would need for an equity stake. I know many people who do or have worked there. At VLSI for a year or two I was responsible for our relationship with ARM and for renegotiating our licenses. So I inevitably follow ARM a bit more closely than any other company. It is clear that Simon is a “safe pair of hands”. ARM is in great shape right now so this is not a CEO change where a major course correction is expected (at least not by me). During Warren’s tenure as CEO, ARM’s partners shipped 40 billion ARM microprocessors. But ARM ships around 8B per year now, so that number will not take long to be exceeded on Simon’s watch.

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View from the top: Brad Quinton

View from the top: Brad Quinton
by Daniel Payne on 03-20-2013 at 3:53 pm
Categories: EDA

Many engineers dream about starting their own company some day, and today I talked with an engineer that has gone beyond the dreaming stage to actually start an EDA company and then get that company acquired. His name is Brad Quinton and the start-up was called Veridae Systems, now part of Tektronix.


Brad Quinton
Continue reading “View from the top: Brad Quinton”

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Interconnect Optimization of an SoC Architecture

Interconnect Optimization of an SoC Architecture
by Daniel Payne on 03-20-2013 at 11:41 am
Categories: Arm, EDA, IP

My last chip design at Intel was a GPU called the 82786and the architects of the chip wrote a virtual prototype using the MAINSAIL language. By using a virtual prototype they were able to:

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Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference

Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference
by glforte on 03-20-2013 at 10:29 am
Categories: EDA, Siemens EDA

This year’s Mentor Graphics user group meeting, User2User, will be held at the DoubleTree by Hilton in San Jose, California on April 25, 2013. The featured keynote presenters include…

  • Dr. Walden C. Rhines, CEO and Chairman of Mentor Graphics, talking about “Organizing by Design”
  • Victor Peng, Senior VP, Xilinx presenting on “The Era of Heterogeneous Architectures and Integration Technologies”
  • Dr. Chenming Hu, creator of the 3D transistor, presenting “FinFET is a Beginning,” showing how FinFET overcomes the impending show stopper limits that device physics imposes

The event will share best practices through customer success stories and technical presentations. Sessions will discuss Calibre, Custom IC/AMS, Emulation, Functional Verification, PBC Flow, Place and Route and Silicon Test. Mentor Graphics customers can register at http://user2user.mentor.com/san-jose-registration-2013.html

See conference agenda:

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Speech Recognition : Can it be the next game changer?

Speech Recognition : Can it be the next game changer?
by gauravjalan on 03-19-2013 at 8:10 pm
Categories: General

The cell phone phenomena has catalyzed the technology growth and coaxed the hardware and software to work more closely. The Apple effect further directed this technology growth to focus on enhanced user experience. The emphasis has been primarily on the display and touch aspects of the designs with limited adoption on other areas. The handsets have moved from buttons to touch display and the next wave under discussion is gesture recognition. Interestingly, direct human to human interaction is mainly through speech while human to machine interface still relies more on passive modes. As a first step to enable this, there is a need for the hardware to respond to the voice commands (pre-defined to start with). A ‘Speech Recognition’ hardware unit is required to interpret the human speech and translate it into text or commands. The applications include call routing for customer service calls, controlling consumer appliances or in-car systems, preparing transcripts and content navigation on cell phone.

Gartner’s annual Hype Cycle Special Report on technologies and trends from cross industry perspective in 2011 revealed that it will take 2 to 5 years for mainstream adoption on this technology.

The main challenges preventing it from moving ahead include –

Developing a programmable user interface – There are a variety of languages across the globe and even for a single language the pronunciation varies widely. The solution should be able to overcome this hurdle with an easy to use interface.

Power – Speech Recognition is a computationally intensive technology requiring several million operations per second. Power dissipation is the key and limits the usage of SW based solutions especially in battery powered devices where continuous use of speech recognition or “Always Listening” as it is popularly known can drain the battery in no time.

While multiple groups might be working towards a solution, one from India claims to have a sophisticated solution available with them. 3iLogic-Designs, founded by seasoned professionals in 2011 recently uploaded multiple videos of their prototype solution. The product name is SimSim and is supposed to be the world’s first ultra compact language & speaker independent, zero connectivity, synthesizable speech recognition core with configurable vocabulary and grammar support. A high level block diagram of the SimSim architecture is given below –

The salient features include –

  • Highly accurate speaker independent Speech Recognition
  • Scalable vocabulary
  • Java Speech Grammar (JSGF) support
  • Based on proven HMM technology
  • Language independent architecture
  • 16Khz/8Khz audio support
  • VAD (Voice activity detection) support with auto calibration for ambient noise
  • Processor-independent, stand-alone operation
  • Independent of external memory type (DDR2/3, SDRAM, SRAM etc.)
  • Very compact solution in terms of memory requirements
  • Implemented with 135K Gates

The list above makes SimSim an ideal solution for localized Vocal-UI solutions for Cell Phones, Digital Cameras, PNDs, MFPs, Watches, Remote Controls, Microwaves, Washing machines etc.

Such a technology enhances user experience for regions with tech savvy population and becomes a prime selling point for the next generation of devices. Along with that it can also drive technology adoption in developing geographies. Countries like India where a majority of consumer market is still untapped primarily because of diversity in the languages spoken and high ramp up learning time on technology, this solution can be a game changer!

The magic of “SimSim” from Arabian Nights is awaiting to open the doors of fortunes once again 🙂