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Cadence ♥ ClioSoft!

Cadence ♥ ClioSoft!
by Daniel Nenni on 02-20-2013 at 5:00 pm
Categories: Cliosoft, EDA

Taking a look at the coveted presentation slots at the CDNLive Conference next month you will see a presentation on Data Management for Mixed-Signal Designs by one of my favorite EDA companies, ClioSoft. Great software, great support, great people, and with customers that are willing to talk publicly about their tools and technology.

Abstract:
Software teams have long used version control and data management systems and they have become an integral part of a software development environment. Practically, no software project, big or small, is started without a software configuration management (SCM) system and methodology in place. Hardware design teams can reap the same benefits by adapting software management techniques to hardware design flows. The paper focuses on how to significantly increase the productivity of analog-mixed signal design teams by improving communication and collaboration between team members and efficiently managing and sharing design data. The paper highlights the challenges of managing large design projects, the pitfalls of using traditional team design techniques and examines the best practices of deploying a design data management system to improve communication, remove bottlenecks, enable reuse, track issues, manage engineering change orders (ECO) and accelerate time to market.

Proposed Takeaways :
Why design teams should deploy a design data management system, what problems it will solve, and how it will improve team productivity and reduce the probability of requiring re-spins. Factors to consider while selecting and deploying a data management system. Best practices in efficiently sharing design data, enabling design reuse and managing last minute changes and ECOs.

Daniel Payne did a nice “Brief History of ClioSoft” write-up HERE. You can also find candid ClioSoft customer’s interviews Daniel did with Qualcomm, Rohde and Schwarz, Tower Jazz, Adesto, Synaptics, Tektronix, Mosys, Avnera, and Moortec.

An even stronger sign of Cadence ♥ ClioSoft is the book Cadence published last year “Mixed-Signal Methodology Guide”. ClioSoft was asked by Cadence to contribute a complete chapter on Design Management. You can see a review of it HERE.

Why did Cadence select you to write the chapter on design management?
ClioSoft has been in the DM business since 1997 and has a large number of customers. We don’t exactly know why they picked us but we would like to think that Cadence had gotten some good feedback about us from their customer base. We pride ourselves on good customer support and try very hard to listen to our customers and provide them with solutions that enhance and streamline their processes. We hope that it is through our efforts that we were chosen to write for the book.

The majority of the other CDNLive presentation slots are taken by the top semiconductor companies around the world so this is quite an honor for ClioSoft. It would not surprise me at all if ClioSoft was on the newly energized Cadence M&A list (hint hint).

If you haven’t registered for CDNLive yet please do so HERE. You can see the full CDNLive agenda HERE. It will be a great conference, I hope to see you there!

Also Read

A Brief History of ClioSoft

Using IC Data Management Tools and Migrating Vendors

Mixed-Signal Methodology Guide: Design Management

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SPICE Circuit Simulation at STMicroelectronics

SPICE Circuit Simulation at STMicroelectronics
by Daniel Payne on 02-20-2013 at 11:18 am
Categories: EDA, Siemens EDA

At the 2010 DACI moderated a panel session on SPICE and Fast SPICE circuit simulation, and one of the panelists was PierLuigi Dagliofrom STMicroelectronics. To get an update on SPICE circuit simulation at ST I read a PDF document at Mentor titled: Improving the Quality of SPICE Simulation Results with Eldo Premier at ST.


ST does IC design for many end-markets, like: Home, auto, health industry and mobile devices. Their AMS IC design flow covers a wide range of tools from Matlab at the system definition stage, down to SPICE at the IC implementation stage:

The CAD group has used the Eldocircuit simulator for many years, then decided to evaluate Eldo Premier, a Faster SPICE tool to see how it compared to Eldo Classic. A list of nine test cases was assembled that were simulated in transient analysis, transient noise analysis, and with language-based designs using the Questa ADMS simulator:

For these nine test cases the measured accuracy of Eldo Premier results versus Eldo Classic was within 1%, so the new simulator accuracy was acceptable.

A comparison of speed improvements show that Eldo Premier could deliver simulation results up to 5X faster than Eldo Classic. Here’s a chart comparing simulation speed across six CMOS test cases:

Modern SPICE simulators need to run on multiple CPUs in order to reduce the overal run times, and using up to 8 CPUs showed good speed improvements.

ST continues to use both Eldo Classic and Eldo Premier for transistor-level circuit simulations, depending on the design size. For netlists with more then 10K devices, they opt to use Eldo Premier. Simulation speed improvements when using language and transistors together also shows speed improvements up to 6X:

Conclusions
ST uses both Eldo Classic and the newer Eldo Premier in their circuit simulations, along with Questa ADMS. The transition from Eldo Classic to Premier was simple because there is no change required on the netlist, the accuracy is the same, and the results come back quicker. With more speed they can do bigger Monte-Carlo simulations that were impractical before.

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TSMC ♥ Cadence

TSMC ♥ Cadence
by Daniel Nenni on 02-19-2013 at 11:00 am
Categories: Cadence, EDA, Foundries, TSMC

In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.

Rick Cassidy, President of TSMC North America, keynoted the Cadence 2013 sales kick-off and had some very flattering things to say about Cadence. The most notable thing, for me anyway, is that TSMC will use more Cadence tools internally. Who cares? TSMC’s top customers care since EDA tools are an important form of communication, especially on the emerging process nodes. Even more important now since the days of multi-vendor reference flows may be a thing of the past.

Two big data points:

[LIST=1]

  • SpringSoft Laker Layout will be replaced with Cadence Virtuoso!
  • HSPICE will be replaced by Cadence Spectre and BDA AFS!

    According to my friends at SpringSoft, the Laker layout tool had a 70% market share in Taiwan including the foundries. Circuit design was still done with Cadence Virtuoso so the link between the two tools is critical. From what I understand, Synopsys will integrate the Laker layout tool intoCustom Designer so the interface between Laker and Virtuoso is in question. Why would Cadence or Synopsys want to spend precious resources supporting that interface? This should bring the Virtuoso market share number up a few points. The other winner in this product transition is Tanner EDA who now owns the affordable layout tool market segment.

    HSPICE has been the gold simulation standard ever since I can remember. I met the Meta Software guys in 1984 when I worked for Data General. We supplied them a machine to get HSPICE ported over for a common customer. A $1M computer was delivered to their garage for the port and the paperwork was signed on their kitchen table. Avant! acquired Meta, Synopsys acquired Avant!, and the HSPICE dynasty continues to this day.

    Magma FineSim was the biggest challenge to HSPICE and one of the reasons Synopsys paid a premium for Magma (my opinion). There were literally thousands of FineSim licenses doing the heavy simulation lifting while HSPICE was used for sign-off. The FineSim customer list included top semiconductor companies, top IP companies, and foundries alike. After the Magma acquisition, quite a few FineSim customers turned to Berkeley Design Automation in order to get the speed of FineSim and maintain two SPICE vendors. SPICE models bridge the information gap between semiconductor design and manufacturing so customers want to know what a foundry uses internally making this is a VERY big opportunity for BDA.

    Before you get too excited about the TSMC ♥ Cadence thing take a look at who is keynoting CDNLive next month: Young Sohn, President & Chief Strategy Officer, Samsung Electronics. Even more interesting, Cadence recently announced the election of Young K. Sohn, president and chief strategy officer of Samsung Electronics to its board of directors. Given that Samsung is TSMC’s biggest threat to their foundry dynasty I find this all intriguing. Certainly better than the reality TV shows that my daughters make me watch!

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    SHIELDing the Android GPU developer in C

    SHIELDing the Android GPU developer in C
    by Don Dingee on 02-18-2013 at 12:52 pm
    Categories: EDA, Siemens EDA

    Repeat after me: SoCs are paperweights if they can’t be programmed. Succeeding with a new part today means supporting a robust developer program to attract and engage as many creatives as possible. NVIDIA has teamed up with Mentor Graphics in just such an adventure. If you read just the press release, you may have missed the real news.

    Continue reading “SHIELDing the Android GPU developer in C”

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    Why IP Must Be Defended

    Why IP Must Be Defended
    by Randy Smith on 02-17-2013 at 7:00 pm
    Categories: General

    A few years ago I was having breakfast with Jim Hogan at our favorite place to meet in Los Gatos. I was CEO of Polyteda and Jim was Chairman so we always had plenty to talk about. This time, however, the talk had turned to protecting a company’s intellectual property (IP). Jim had brought up the topic in the context of the looming legal battle between Sonics and Arteris. Unfortunately, I steered the conversation back to my EDA roots and the Cadence-Avant! legal battle. I would have learned more if I had just listened. Semiconductor IP is not quite like software IP as there are different methods of protection, such as mask works, and patents may be easier to spot in circuits than in code.

    Recently Tela Innovations, where Jim Hogan is on the board of directors,filed two actions against a group of companies who are in the mobile phone industry alleging that these companies had illegally used Tela’s patents in their products. I was surprised by the initial reaction of some in the EDA community remarking that Tela was suing its customers. Some sites have since edited or even removed some of their earlier comments. The simple fact is that if you are an IP company and you have evidence that some company is using your IP without proper licensing you MUST defend your IP. It is obvious in other industries where stores prosecute shoplifters, so why would IP be any different? They’re not yourcustomer if they are stealing from you.

    Why do I use a strong term like “must”? Well, think about all the obligations that the company has; or, as board members and executive think of it – think of all of your stakeholders. First, you have an obligation to your investors. They put money into the company on the promise you were going to build something of unique value. For an IP company your patent portfolio represents a significant chunk of your company value and that value is partially owned by the investors. You must protect them. Secondly, you have paying customers to whom you sold a license to your IP. If you let others use it without paying for it is that fair to them? You also have your own employees to protect. If the company fails because the IP becomes free to use by anyone with the temerity to use it without paying for it then the employees may lose their jobs and the employee stock options become worth less (or worthless) as well. Even the community the company operates in will be damaged if the company is not there to continue to provide benefits to that community. For those that believe in karma, you may also feel that cosmic justice plays a role as well.

    Tela’s filing with the U.S. International Trade Commission (USITC) alleges that various corporations including HTC, LG, Motorola Mobility, and Nokia have imported products which infringe seven of Tela’s patents. A similar action was also filed in federal court in Delaware. Tela can hope for a somewhat quick resolution from the USITC because that body is in place to stop trade practices before the violators gain much benefit from their actions. But, the companies Tela is bringing the actions against have a lot resources and no doubt the ability to drag this out some if they choose. Presumably, Tela is in a strong enough position to fight this battle a long time if necessary.

    I cannot declare that Tela is right or that Tela will be victorious. I have not had the chance to read all of the filings and supporting evidence. The documentation is substantial so passing judgment now would be like voting on the voluminous Obama Care healthcare act without actually reading it. Hmmm… well, uh, anyway my heart tells me that Tela certainly believes it is correct in taking this action. Besides my longtime relationship with Jim Hogan, I believe in the character of others at Tela (Scott Becker, Drumil Ghandi, etc.) whom I worked very closely with at Artisan Components.

    I have a background in semiconductor IP having worked at TriMedia Technologies and Silicon Architects in addition to working at Artisan Components. I also was a co-founder of Tangent Systems, which is where part of the code stolen by Avant! from Cadence originated. I am sensitive to protecting a company’s IP. If Tela’s allegations are indeed accurate the whole of the IP industry, and probably the EDA industry as well, needs to have Tela prevail, and sooner rather than later. Otherwise, many more alleged thefts will occur.

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    ISSCC 2013: Circuit Design Using FinFETs!

    ISSCC 2013: Circuit Design Using FinFETs!
    by Daniel Nenni on 02-16-2013 at 8:00 pm
    Categories: EDA, Events, IP


    One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:

    ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following the invention of the transistor in 1947, there was a developing interest in transistor circuit design. This coalesced in 1954, with the creation of the first “Conference on Transistor Circuits”, held in Philadelphia, sponsored by the IRE, one of the predecessors of the IEEE. Since then, transistor-circuit design which evolved into integrated-circuit design has changed the world like no other technology ever has. Propelled by this sixty-year history, ISSCC 2013 will provide a special opportunity for looking back to the future, toward further exciting developments in solid-state circuits and systems. ISSCC remains the premier forum in the world where circuit innovations are presented. In this role, ISSCC will continue to (em)power the future!

    The advanced program is HERE, if you want to avoid me do NOT attend these sessions:

    T4: Circuit Design using FinFETs
    After HKMG, FinFETs are a powerful yet disruptive technology to enable continuous scalingfollowing Moore’s law. The disruptive nature arises from both the 3D structure and the quantization on width choice. FinFETs require new design skills to trade-off among PPA (powerperformance-area) and to conduct circuit-process co-optimization. Salient advantages ofFinFETs include: increased driving capability per footprint area, better control on short-channeleffect, subthreshold slope, and less requirement on channel doping. Thus, threshold voltagecan be reduced, which enables a reduction in supply voltage and thus power consumption or increase of performance speed.

    The tutorial will focus on critical issues of FinFET design: It starts with a crisp comparison ofplanar vs. 3D FinFET devices and the associated SPICE modeling. Next, logic design is presented,including effects on standard cells, I/O circuitry, and ESD. Then, the subjects of SRAMand analog/mixed-signal design are treated in detail. Digital chip-level design that requiresmethodology enhancement and new CAD tool features are carefully discussed. The tutorialwill enable CMOS designers to systematically comprehend circuit design using FinFETs.

    As I have mentioned before, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Attend every FinFET seminar, read every FinFET paper, stay glued to SemiWiki because FinFETS will set the semiconductor ecosystem on fire. FinFETs will keep the mobile world powered up, FinFETs will set the foundries apart. It’s coming, believe it.

    ES3: High-Speed Communications on 4 Wheels: What’s in your Next Car?
    Communications inside vehicles is experiencing a growing demand due to applications likeinfotainment, driver assistance, safety systems and diagnostics, requiring data-rates beyondwhat is offered by current solutions.

    Considering that cabling is the third highest cost factor and the third heaviest component inthe car, there is a clear need to go beyond the current low data-rate solutions and convergeto a high data-rate backbone network. Solutions, both electrical and optical, are being proposed by car-makers and silicon manufacturers. The evening session will give an overviewon the status and outlook on an emerging market that is already shipping 650 million communication ports per year.

    One of the biggest disappointments at CES this year was the cars of the “future”, we can do better.

    EP3: Empowering the Killer SoC Applications of 2020

    A distinguished panel from global industry and academia will debate the nature of systemsdriving the killer applications of 2020. Can we forecast the future killer applications? We havehad the computing revolution, then communications, and now the sensor era. Are sensorsdriving the next killer applications? Are there any other revolutions in sight? What circuitsand system innovations can ISSCC bring forward for the next killer applications? What technology elements, device structures and memory architectures are required? Should we continue with silicon technology and find breakthroughs through system architecture, algorithms, SoC integration and packaging? Or should we prepare for “beyond silicon” technologies? Are any beyond-silicon technologies realistic for the future?

    For those of you who don’t know, Fisherman’s Wharf has great seafood and is a Cable car ride away. Scoma’s is my favorite but just eating a bowl of cioppino on the waterfront is fine too. The weather looks good but bring an umbrella because it is San Francisco and you just never know. I have an ISSCC umbrella from last year somewhere.

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    Aldec Delivers Leading Verification Methodologies!

    Aldec Delivers Leading Verification Methodologies!
    by Daniel Nenni on 02-14-2013 at 8:15 pm
    Categories: Aldec, EDA

    For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

    I first met Aldec at DAC and was very impressed by the focus they have on training and education. You can find a nice list of white papers HERE, multimedia webinars, videos, and demonstrations HERE, application notes HERE, and tutorials HERE. And of course the Aldec SemiWiki landing page is HERE with coverage by Daniel Payne and Don Dingee.

    Aldec has an important DO-254 Training Event (Webinar)coming up that we are all invited to:

    DO-254 Verification Strategies

    Date:Thursday, February 21, 2013
    Time:11:00 AM – 12:00 PM PST
    Presenters:
    Louie DeLuna – Aldec DO-254 Program Manager
    Daniel Conway – X-Tek DO-254 Consultant

    Abstract:
    As a best-practice standard, efficient ASIC and FPGA project planners will allocate 1/3 of the project cycle to design and 2/3 of the project cycle to verification. The best of these planners will bias toward even more verification-hours and innovative verification strategies whenever possible, because the great reality of schedule-time allocated to verification is that THERE’S NEVER ENOUGH TIME.

    When an FPGA or ASIC is destined for an avionics product, effective design of that DO-254-qualified device is even more dependent-upon good verification strategies and practices. Good verification strategies will use those precious hours more effectively – and will also consistently prove to be more useful when combined with a comprehensive exploitation of well-written requirements and compliance with a well-constructed verification process, planned in advance of the work.

    REGISTER HERE

    In this webinar, we will discuss various verification strategies and how they can be applied to successful verification of a design in a DO-254 Levels A/B flow.

    Agenda:

    • How and where verification fits into the overall process
    • Verification Strategies
    • Ad-hoc testing
    • Directed testing
    • Constrained random testing
    • Verification Architectures
    • Driver – Waveform
    • Auto-checking
    • OVM/UVM
    • Code coverage and its proper usage
    • Documentation and reviews
    • Test plan vs. test cases
    • How to pass the audit
    • Q & A

    Aldec is a proven EDA solutions provider delivering leading verification methodologies that support the latest language standards enabling their customers to grow while leveraging evolving technologies. Definitely worth a look, their corporate website is HERE.

    RTCA/DO-254 and EUROCAE/ED-80 are means of compliance for the development of airborne electronic hardware containing FPGAs, PLDs and ASICs. FPGA design and verification under DO-254 guidelines is a rigorous undertaking, and requires special features and capabilities from design, simulation and hardware verification tools.

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    Patenting in the (Resistive Memory) Material World

    Patenting in the (Resistive Memory) Material World
    by Christie Marrian on 02-14-2013 at 8:10 pm
    Categories: IP

    (with apologies to George Harrison) Two recent Blogs over at ReRAM-Forum.com have focused on the latest in the IP field, particularly as it affects resistive memory. A high level overview of who is patenting what suggests a healthy amount of R&D is going on in the field. But looking a little deeper suggests there is much overlap amongst some supposedly key patents. Perhaps this is inevitable for an emerging technology but people familiar with the field point out that this in fact an impediment to the introduction of the new technology. On the other hand, the belated arrival of PCRAM suggests this can be overcome, at least during the early stages of a product gaining traction in the market place. Unfortunately, these days, it is a sign that a technology has gained a foothold in the market when the lawsuits start flying!

    Alerted by Beth Martin’s Blog here at SemiWiki, we’ve also looked at the impact of the HR. 1249 aka America Invents Act (Image shows President Obama signing the act into law along withand the Sponsors andstudents of Thomas Jefferson High School, Alexandria, VA). Under the Act, the US is changing from a First to Invent system to a First to File (actually First Inventor to File possibly for reasons of constitutionality). This legislation was heavily sponsored and lobbied for by the Tech Lobby and all sorts speculation has ensued that this is a plot to stifle the small entrepreneur. I’m not totally convinced and there are upsides to the Act such as (the promise of) a faster (1 year) examination timeline, filing fee discounts for the new class of ‘micro entities’ (individuals and universities) and revised post grant procedures. Nonetheless, I’m sure the litigation lawyers won’t be going out of business anytime soon.

    Interestingly a couple of resistive memory related job openings have appeared recently; one on each side of the pond. While not as big of a story as the famous ReRAM job position advertised by SanDisk last year, it good to know that people are still hiring.

    On the technical side, we are taking a look at IBM’s MIEC BEOL access device for ReRAM/CBRAM and PCRAM. This almost seems to be the ‘perfect’ diode with an enormous on/off current ratio. IBM has been quite open with performance and processing data although the composition of the material stack is not made clear. Which takes me back to searching through Patents and Patent Applications!

    Christie Marrian, ReRAM-Forum Moderator and Real (Court) Tennis player

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    Functional Check List in Verification

    Functional Check List in Verification
    by guruvadhiraj on 02-13-2013 at 8:25 pm
    Categories: General

    This article tries to bring out the advantages of having a functional check list. The objective is to make verification as robust as possible. Functional check list ensures the complete coverage of hardware block that is designed. This may to an extent help software developers. Creation of test plan with functional check list as the base will result in creating a test plan which covers end to end of hardware block. Functional check list might already be existing in some of verification process as on today but some sections audience might have missed out.

    First lets describe the role of having a check list of functionality that hardware block is designed to perform. The intention of this step is to make sure that none of the functionality of hardware block is missed and the coverage of various scenarios. Secondly, of late I have seen some influence of software requirements having some impact on verification. Let us take an example of uart, if the hardware engineer is having an input that software engineer will use ‘x’ baud rate, then there is possibility that that hardware engineer will make sure that ‘x’ baud rate works perfectly fine and few baud rates around that baud rate. For other baud rates, he may or may not do the verification which could be because of two reasons

    [LIST=1]

  • Time constraint
  • Necessity

    If the reason was former then it is understandable though it is not convincing. If the reason is later then it is advisable to change the perception.

    Functional check list helps in identifying the test case/scenario’s that was missed during verification. In the above case of UART , if the verification engineer misses some of the baud rates then comparing the result of verification to functional check list will bring out the missed scenarios.

    It also helps in identifying the corner cases, random and regression testing before proceeding with the verification/test plan.
    Typically Asic Design has the following steps

    [LIST=1]

  • MRD
  • Architecture specification
  • Design Specification
  • Verification Plan
  • RTL Design
  • Functional verification
  • Synthesis
  • Physical Design
  • Timing Analysis
  • Tapeout

    Functional check list falls between step3 and step4, i.e. when design specification is ready , functional check list is created.

    [LIST=1]

  • MRD
  • Architecture specification
  • Design Specification
  • Functional Check list
  • Verification Plan

    Let us see some simple implementation by having counter as an example. Assume that this counter can perform incrementing count and decrementing count, Interrupt signal when count matches compare value, different clocks and Auto Reload.


    Functional check list

    [LIST=1]

  • Increment count with basic/default clock rate
  • Different Compare value(actual values can be written) and interrupt generation
  • Different clock rates of a,b,x,y,z
  • Auto reload with different values
  • Decrement count with basic/default clock rate
  • Different Compare value and interrupt generation for down counter
  • Different clock rates of a,z for decrement count
  • Auto reload with different values
  • Interrupt disable

    Above list describes the functionality of the counter. we can find that some of them in the above list is repetitive for e.x : different clock test when counting up and counting down. This is to ensure that hardware block is tested in all scenarios as much as possible.
    There can be two more list called as negative list where negative scenario’s can be mentioned and regression list. Negative and regression list is not mentioned here as there is not much for the counter module.

    Before starting the verification we can have

    [LIST=1]

  • Functionality list
  • Negative list
  • Regression list

    As the complexity of hardware increases so is the checklist. When there are signals interfaced to the hardware block, it can be written along with one of the functional list. As explained in counter there is interrupt signal when counter matches compare value. Therefore this can be further written as two columns.

    [TABLE] border=”1″
    |-
    | style=”width: 319px” | Functional list
    | style=”width: 319px” | Signal name
    |-
    | style=”width: 319px” | Different Compare value and interrupt generation
    | style=”width: 319px” | INT0 (Interrupt signal name)
    |-

    Table 1

    This list helps the verification engineer in writing the test plan and test bench. This gives overview of verification engineer’s understanding of the hardware block. When the hardware complexity increases , time spent on this activity would be more but significantly reduces the effort in feature extraction. With this kind of approach Integration of blocks becomes much easier.


    Let us take another example which does the generation of signals. In this example Consider Block X having 3 registers as reg_a, reg_b, reg_c. The functionality of this block is to generate signals based on programming the registers. This block may not have much functionality like the counter but signal generation is the main task of this block. In such cases we can the functionality list as mentioned below

    [TABLE] border=”1″
    |-
    | style=”width: 296px” | Functional list
    | style=”width: 295px” | Signal to be asserted
    |-
    | style=”width: 296px” | Reg_a =1
    Reg_a =0
    | style=”width: 295px” | X_a =1
    X_a =0
    |-
    | style=”width: 296px” | Reg_b =1
    Reg_b =0
    | style=”width: 295px” | X_b =1
    X_b =0
    |-
    | style=”width: 296px” | Reg_c =1
    Reg_c =0
    | style=”width: 295px” | X_c =1
    X_c =0
    |-
    | style=”width: 296px” |
    | style=”width: 295px” |
    |-
    | style=”width: 296px” | Different clocks x,y,z
    Reg_a =1
    Reg_b =1
    Reg_c =1
    | style=”width: 295px” | X_a =1
    X_b =1
    X_c =1
    |-
    | style=”width: 296px” |
    | style=”width: 295px” | X_a =0
    X_b =0
    X_c =0
    |-

    Table 2

    Looking at the above table, second column gives the opinion of expected result. The answer is yes . For models such as the one mentioned above signal generation is the main functionality.

    These are basic examples that are discussed. There are many hardware blocks with complex systems and complex interfaces. The above table becomes complex with the complexity of the module/chip.

    The next question that would arise is why not expected result as one of the columns in counter block?

    Expected results can be included in test plan where as the functional check list concentrates on functionality coverage
    To put it in simple words, with the functional check list chances of missing the corner cases is less
    Is functional list different from Feature Extraction?

    Objective of the functional list and Feature Extraction is same. In this case, feature extraction can be considered as subset of functional list.

    Functional check list will help in systematic approach to verification. It will help in identifying the test bench requirements and approach to functional verification. It is up to verification Engineer to decide the usefulness of this approach.

    This is a suggestion. Comments and feedback are welcome. I can be reached at LINKEDIN :
    in.linkedin.com/pub/guruprasad-pv/9/947/9b1

    guruvadhiraj@gmail.com/gurushesha@gmail.com