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Carbon CEO on Advanceed ARM based SoC Design!

Carbon CEO on Advanceed ARM based SoC Design!
by Daniel Nenni on 05-15-2013 at 10:00 am
Categories: Arm, EDA, IP

Carbon Design drives a lot of traffic to SemiWiki. Actually, it’s ARM driving traffic to the Carbon landing page since Carbon and ARM work closely together. When we blog about designing with ARM IP droves of people click over. Seriously, DROVES of people. Rick Lucier has deep EDA experience and has led Carbon as CEO for the past seven years so you are going to want to read this one:

Q: What are the specific design challenges your customers are facing?
Carbon’s 50+ customers are primarily concerned with accelerating the development of advanced SoCs containing ARM processors. As part of this we see them facing the following challenges:

[LIST=1]

  • SoC Performance Optimization. Choosing the right IP and proper configuration is a difficult task given the complexity of today’s processor, fabric and memory controllers. It’s a challenge to balance the performance demands while meeting the power budget. This task used to be driven with spreadsheets and back of the envelope calculations. Now however, there is a need to accurately model the critical components in order to validation assumption and meet the market requirements, budget and time constraints.
  • Early debug and development of firmware. Being able to debug and develop “hardware aware software” well ahead of silicon yields a much shorter design cycle. Software is the long pole in the tent for design schedules and it is critical for customers to have access to a solution that provides both accuracy and performance. Solutions such as emulation and other hardware prototypes are too costly and difficult to deploy across the growing number of developers and this creates a bottleneck for design teams.
  • Provide a solution to allow tighter design collaboration within our customers’ eco system. Design times continue to shrink while the complexity of products continues to grow. Part of that complexity is a larger eco system contributing to the end product. In order to meet the time constraints, more people need to have access to the system before silicon to ensure that it meets market requirements, proper integration of 3[SUP]rd[/SUP] party subsystems and the complete software stack is optimized.

    As with all EDA vendors the goal is to identify current and future bottlenecks and provide a solution to remove them thus shortening the design cycle.

    Q: What does your company do?

    Carbon provides customers the ability to quickly assemble virtual prototypes that remove the traditional tradeoff between accuracy and performance. This saves months off the SoC design cycle and ensures that software will run on silicon the first day it shows up in the lab.

    Q: Why did you join your company?

    I have spent over 25 years in EDA before joining Carbon and have witnessed the challenges EDA companies have had in addressing the software bottleneck facing design teams. Carbon had an interesting approach in solving that problem which was very attractive – not a pure EDA company, but not a pure IP company. This approach continues to mature and with the combination of our tools, partners and business model will make virtual prototyping the norm and augment traditional hardware assisted simulation solutions in addressing the software bottleneck. I believe this approach will have a significant impact on EDA.

    Q: How does your company help with your customers’ design challenges?
    Our customers use our products to meet the following design challenges:

    [LIST=1]

  • Remove the model barrier.Model availability has always been a barrier virtual prototype adoption. Carbon’s IP Exchange is a web portal (www.carbonipexchange.com) that removes this barrier by enabling customers to easily configure IP from various IP vendors such as ARM, Arteris, Cadence etc… The portal then automatically generates 100% accurate models. Over 5000 models have been generated by our customers using this portal. For internal IP or design blocks not available from Carbon IP Exchange, we offer the industry’s leading virtual model compiler capable of generating a 100% accurate model from any Verilog or VHDL design.
  • Accelerate the creation of virtual platforms.Models are great to enable virtual prototype adoption but assembling these blocks together with necessary bare metal and OS level software in order to use them can present a time consuming challenge. To meet this challenge and get designers up and running quickly, Carbon has assembled over 80 Performance Analysis Kits (CPAKs) which consist of a variety of leading based processors, memory controllers and interconnect fabric with the ability to run various operating systems and benchmarks. This provides an excellent starting point to build a custom virtual prototype trimming weeks and months off the traditional “start from scratch” approach. These CPAKS can also be downloaded from Carbon IP Exchange.
  • Deliver a unified virtual platform that can be leverage across disciplines from architectural analysis to software development. Carbon’s SoC Designer Plus is a unique virtual prototype solution. It is the only tool which enables the same virtual prototype to be used for architectural exploration, firmware development and OS level software debug.. This is enabled by our unique Swap & Play technology. A design in SoCDesigner Plus can boot an OS in seconds using an abstract representation of the system and then switch to a 100% accurate representation at any breakpoint to enable detailed debug and analysis. With Carbon’s there is always a path to accuracy to ensure that the software will run on first silicon. Our pure software solution (no hardware assisted solutions) allows the prototype to be easily exchanged within our customer’s ecosystem and is a financially attractive alternative to traditional hardware assisted solutions.

    Q: What are the tool flows your customers are using?

    For architectural analysis the old traditional spreadsheet approach is thing of the past given today’s complexity. To address this need there is a mix of internal tools and commercially available tools such as Carbon. For customer’s that require precision (100% accuracy) Carbon is the solution of choice. For firmware development often times FPGA prototypes and emulation are used but we see a strong movement towards virtual prototypes since the platform can be delivered earlier and to a larger audience in a cost effective manner. The requirement is to have accuracy and performance which is unique to Carbon’s solution.

    Q: What will are you focusing on at the Design Automation Conference this year?

    At this year’s DAC we will be focusing on our solutions around the new ARM A57 processor.

    Q: Where can SemiWiki readers get more information?

    More information on Carbon’s solutions can be found at www.carbondesignsystems.com, www.carbonipexhange.com and by subscribing to our blog at http://www.carbondesignsystems.com/virtual-prototype-blog/

    Carbon Design Systems offers the industry’s only unified virtual prototype solution along with the leading solution for accurate IP model creation. Carbon virtual prototypes can execute at hundreds of MIPS and with 100% accuracy to enable application software development, detailed architectural analysis and secure IP model distribution. Carbon’s customers are systems, semiconductor, and IP companies that focus on wireless, networking, and consumer electronics. Carbon investors include Samsung Venture Investment Corporation and ARM Holdings. Carbon is headquartered at 125 Nagog Park, Acton, Mass., 01720. Telephone: (978) 264-7300. Facsimile: (978) 264-9990. Email: info@carbondesignsystems.com. Website: www.carbondesignsystems.com.

    lang: en_US

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    Methodics CEO on Managing Design Quality!

    Methodics CEO on Managing Design Quality!
    by Daniel Nenni on 05-14-2013 at 8:05 pm
    Categories: EDA, Perforce

    Methodics is new to SemiWiki and I have to tell you I’m really enjoying working with them. Their office is in a great location and the inovation spirit runs strong. Simon Butler is an interesting guy. He first started in EDA with HLD (acquired by Cadence) and was a founder at Sabio Labs (acquired by Magma). In between those startups he found time to work on FFT processors at Fujitsu, 64bit Microprocessors with Sandcraft, and was the architect behind Cadence’s Virtuoso Custom Design product (Cadence’s solution that wrapped a qualified methodology around Cadence’s mixed-signal/analog tools). His interest in software configuration management led him to develop VersIC and to get involved in the data management space, an area (in his opinion) ripe for innovation.

    Q: What are the specific custom IC design challenges your customers are facing?

    Managing and sharing data across multi-site teams, managing the quality of releases in terms of completeness and verifications, and ultimately assembling SoC designs.

    Q: What does Methodics do?

    Methodics develops Semiconductor and System Specific DM tools that leverage popular software configuration tools such as Subversion and Perforce. Our innovation was to build SoC specific tools on top of these proven DM solutions so that customers can use their existing data repositories and implement a common data management infrastructure across all their design. A common repository for their RTL data, Design Data, software etc means that making releases, automating SoC assembly and harvesting analytics on a single platform a reality.

    The Methodics portfolio of tools includes:

    1. VersIC – Analog/Mixed-Signal data management
    We provide Cadence and Synopsys solutions to integrate the analog/mixed-signal design environment into the popular Subversion and Perforce configuration management tools

    2. Evolve – Digital verification and release management
    Evolve manages all aspects of digital design and verification. It includes a framework for running tests and regressions, an integrated continuous-integration style release server, and coverage management features. Evolve tracks all verification activity in a SQL database, and ties it all together with live testplans and reporting dashboards. Evolve implements all items that most front-end design professionals wish they had in their verification infrastructure, out of the box.

    3. ProjectIC –IP/SoC Management
    ProjectIC is an enterprise IP management platform. ProjectIC enables true IP re-use across the organization by providing a flexible, searchable, IP catalog, integrated IP usage tracking, workspace management and IP permissions. With ProjectIC, companies can put together integrated, robust flows for sharing IP across teams – saving time, money and significant management overhead.

    Q: Why did you start Methodics?

    After we left Cadence, myself and my cofounder (Fergus Slorach) had a busy consulting business in the mixed-signal design space 2000-2006 developing new EDA tools, integrating existing 3rd party tools into the Custom IC design environment and implementing mixed-signal CAD methodologies. Integration of Perforce and Subversion was a common theme during that period so we wrote VersIC as an initial foray into the DM space. This business has grown from a Mixed-Signal/Analog data-management solution to a full enterprise solution for IP/SoC assembly

    Q: How does Methodics help with your customers’ custom IC design challenges?

    Methodics leverages industry standard configuration management tools such as Perforce and Subversion to track changes, manage releases and build workspaces for large multi-site teams. Methodics includes data management clients for both analog and digital design teams including dashboards with integration metrics, test history all tied to releases.

    Q: What are the tool flows your customers are using?

    Our customers use a variety of mixed-signal flows. We have customers focused only on analog design and those people are typically using VersIC standalone. Some of our customers have “Big A, Little D” methodologies with a single place and route block in the design. For those customers the ability to maintain both their analog and digital data in a single repository, and use the standard software clients for Subversion/Perforce make for a very convenient methodology. We see a lot of traction with our VersIC/ProjectIC tool for managing these blocks at either the IP or library level. Finally amongst our “Big D, Little A” customers we see a lot of VersIC/Evolve usage for managing the design data with ProjectIC used to assemble the overall SoC.

    Q: What is the roadmap for Methodics?

    Methodics acquired Missing Link Tools in mid 2012 and have been working on integrating their multisite RTL test history and regression management tools into our IP/SoC management solutions. Our vision is a common platform for managing analog and digital designs including a full test/regression history database that associates every release with the set of failing/passing regressions.

    Q: Will you be at the Design Automation Conference this year?

    Yes, we’ll be in Austin this year demoing our VersIC Analog Regressions and Release tool suite, as well as our analog/digital DM solutions and our IP/SoC assembly platform.

    Q: Where can readers get more information?

    www.methodics.com

    http://www.semiwiki.com/forum/content/section/2230-methodics.html

    Methodics, Inc is a leading developer of design data management (DM) tools for IC’s, and is the first company to offer a tool suite for global IC design collaboration. Providing standard software configuration management (SCM) functionality on an advanced modular platform that enables hardware design methodologies in a version-controlled context, the new Methodics solution represents a revolutionary approach to global design collaboration.

    Methodics Inc has developed the VersIC 2.0 platform, a DM tool that abstracts the backend database allowing easy integration of industry standard SCM tools and facilitating software-style methodologies in the custom IC design environment. The VersIC 2.0 platform allows plug-in modules that extend the data-management functionality to design reviews, diff/merge of cellviews, continuous integration methodologies and others, enhancing the global design collaboration experience for its users.

    lang: en_US

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    Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs

    Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs
    by Daniel Payne on 05-14-2013 at 6:27 pm
    Categories: Ansys, Inc., EDA

    I love it when my Acura goes months and months without any major repair issue or computer-related glitches. Cars or networks only become reliable when they are designed and built for reliability. Freescale designs SoCs for advanced automotive and networking applications, and their engineers know much about the topics of power, noise and reliability for these demanding environments.

    Continue reading “Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs”

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    Qualcomm JEDEC Mobile Keynote: Memory Bandwidth and Thermal Limits

    Qualcomm JEDEC Mobile Keynote: Memory Bandwidth and Thermal Limits
    by Paul McLellan on 05-14-2013 at 4:37 pm
    Categories: General

    I went to some of the JEDEC mobile conference a couple of weeks ago. The opening keynote was by Richard Wietfeld of Qualcomm called The Need for Speed.

    He emphasized that smartphones are really setting the pace these days in all things mobile and internet. Over 1/3 of access is on smartphones now. Over 4/5 of searches on smartphones are spontaneous, half of smartphone users use them while watching TV (and I’ve seen numbers elsewhere that 10% use them during sex). Smartphones have to be always-on, always-up-to-date and power-efficient. It’s a tall order.

    Meanwhile the mobile ecosystem is preparing for 1000X increase in traffic. It doubled in just the last 12 months so if keeps that up for 10 years we’re there. One way this will happen is using picocells, which are basically the size of a cell-phone with either hard-wired or wireless backhaul. They need to be pretty much self-configuring. These will be deployed on the scale of individual rooms, cafes, stores etc.


    One of the big challenges in smartphones is memory bandwidth. As an example, as the number of pixels on a cameraphone increase, the memory bandwidth needed to process video and still photographs goes up. But there are limits on how much of that bandwidth can be used and for how long. In a very real sense there is a tradeoff between DRAM bandwidth and power consumption.

    There are 3 limitations:

    • limited battery life
    • temperature of the “skin” of the phone gets too hot to touch (you can’t hold it)
    • temperature of the chips gets too high leading to reboot or total failure


    Simulating the DRAM bandwidth with a model of the case leads to the conclusion that you can only run at 10GB/s for 10 minutes or at 50GB/s for just 2 minutes before the thermal limit is reached. It is not just battery life that is creating a huge challenge on the power front.

    So future memory needs are in the 10s of GB/s, power consumption needs to be low for battery and thermal reasons, packaging needs to get multiple die (or perhaps one day memory on logic 3D), the radios in the phone and the memory need not to interfere with each other…and, of course, it all needs to be really cheap. Quite a challenge.

    Richard’s full presentation is here (may need to be registered with JEDEC).

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    Chip and I/O Modeling for System-level Power Noise Analysis and Optimization

    Chip and I/O Modeling for System-level Power Noise Analysis and Optimization
    by Daniel Payne on 05-14-2013 at 4:13 pm
    Categories: Ansys, Inc., EDA

    Cornelia Golovanovworks at LSI Corp in Pennsylvania and is an EMI expert that provides EDA tool and methodology advise to design groups. She earned a PhD in microelectronics and radioelectricity from the Institut national polytechnique de Grenoble, and joined Lucent out of school 12 years ago. We had a chance to talk by phone about her work and also DAC plans.

    Continue reading “Chip and I/O Modeling for System-level Power Noise Analysis and Optimization”

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    Jasper Low Power Verification App

    Jasper Low Power Verification App
    by Paul McLellan on 05-14-2013 at 1:58 am
    Categories: EDA

    Today, Jasper announced their new Jasper-Gold Low Power Verification App. This is focused on verifying low power designs with multiple power domains, voltage islands, power shutoff, clock shutoff, and all the other techniques used for reducing power. Of course power is the main driver of SoC design these days, whether it is for mobile chips (in which extending battery life is paramount) or high performance chips (where power limits how fast the design can be clocked). Very few designs are lucky enough not to require aggressive power management.

    The JG-LPV App reads the RTL description and creates an internal power-aware formal model in accordance with the power partitioning specifications. The new App verifies power optimization structures, power management circuitry, power sequencing, and works with other JasperGold Apps to verify that the power optimizations do not corrupt the original design functionality. The JG-LPV App supports the standard UPF and CPF power intent specification formats. The App’s automated approach, together with the exhaustive nature of formal verification, can reduce verification time, cost, and risk compared to traditional power-aware verification approaches.

    When adding low power features to a design, the basic functionality should not be affected. But making this happen is complex since power mode transitions often require complicated sequencing (for example, to minimize inrush current when powering a block back up) or controlling the changes in voltage and frequency over a significant number of clock cycles during DVFS (dynamic voltage and frequency scaling). Also there are requirements for introducing level shifters, retention registers and isolation cells that if done incorrectly can result in non-functional designs. All this needs to be checked.

    Simulation is always one option, of course. But by its very nature, it is obscure corner cases in power management that are likely to be troublesome. Obscure corner cases are just the areas where formal techniques, proving that the design is correct, are most likely to escape detection and cause failure.

    The LPV App works with other JasperGold Apps to perform a complete analysis of the design. Power is a chip-level attribute that inevitably interacts with many other areas of the design.

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    SOCFIT, Circuit Level Soft Error Analysis

    SOCFIT, Circuit Level Soft Error Analysis
    by Paul McLellan on 05-13-2013 at 2:50 pm
    Categories: EDA, IROC Technologies

    I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

    That is where IROC Technologies SOCFIT tool comes in. It takes all the data from the type of silicon analysis with real neutrons, and uses it to analyze the way that the various cells on the chip have been hooked together to provide reliability estimates. SOCFIT quickly and accurately calculates the failure rate (FIT) and various derating factors for the SoC. It works from either an RTL or a gate-level representation of the design.


    SOCFIT uses the foundry’s SER database for FIT and derating simulation. It can handle very large designs with tens of millions of flops. It then provides an extensive report detailing the contribution of each cell in the design to the overall FIT rate and details of derating. There is a smart fault injection simulation for application derating. SOCFIT is available as a tool but usually, at least the first time, design groups work with IROCtech experts to both get good results and to learn how to interpret them.


    How much it is worth investing to make the design more reliable and less sensitive to SEE errors is an economic one, and depends on the end-market. Satellite electronics might justify triple redundancy and voting since they have to survive in a more hostile environment than on the ground. Making a cell-phone that reliable is just not worth the cost since they are not mission critical and will most likely crash regularly due to software bugs and other issues, not due to cosmic rays. And a phone only has to last a few years.

    Automobile electronics is one of the areas most focused on reliability. Cars have to last for twenty years, operate in deserts and Alaskan winters, and while it doesn’t matter too much if your radio reboots due to a particle upset, the engine control ECU(s) are another thing. Medical electronics is another area which cannot tolerate much unreliability.

    As transistors get smaller and smaller, and the power-supply voltages continue to decrease, the currents that high energy particles can induce are more and more likely to cause SEE upsets. So this isn’t a problem that is going away, it is a problem that is going to continue to get worse.

    A case study on SOCFIT is here. The datasheet for SOCFIT is here.

    IROCtech will be at DAC in booth #1738.

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    UVM/SystemVerilog: Verification and Debugging

    UVM/SystemVerilog: Verification and Debugging
    by Daniel Payne on 05-13-2013 at 2:45 pm
    Categories: Accellera, Aldec, EDA, Semiconductor Services

    At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner rather than later.
    Continue reading “UVM/SystemVerilog: Verification and Debugging”

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    Sonics-ARM Form A Potent IP Combination

    Sonics-ARM Form A Potent IP Combination
    by Randy Smith on 05-13-2013 at 1:30 pm
    Categories: Arm, IP, Sonics

    Recently, Sonics and ARM entered into an agreement whereby ARM licensed a significant portion of Sonics’ patent portfolio. Sonics, Inc. is one of the leading providers of connectivity IP often referred to as network-on-chip, or NoC. ARM is the leading provider of processor intellectual property (IP). The potential scope of their relationship is huge:

    “A broad IP ecosystem is critical for the successful deployment of SoCs,” said Tom Cronk, executive vice president and general manager, Processor Division, ARM. “The agreement to license Sonics’ interconnect patents and to support Sonics on their next-generation interconnect and low power management is an important step in strengthening the ecosystem. Sonics and ARM have a clear vision for the future of IP technology, which we look forward to realizing together.”

    Most of the leading edge designs today consist of these two components (processors and NoC) plus other modules including memories and various specialized blocks for interfaces (e.g., USB, LVDS) and data processing (e.g., motion estimation). From an architectural perspective, the processor and NoC choices are probably the most critical decisions a chip architect needs to make. That ARM and Sonics are so obviously interested in cooperating with each other is significant and fortuitous for their customers and the industry in general.

    While the formal announcement did not contain any financial information, it did indicate that a large number of patents were licensed to ARM – 138 patents. Recent deals in this area usually value patents in the range of $200k to $700k per patent (e.g.,MIPS-Imagination, Google-Motorola, Nortel Patents). While these more public deals involved large corporate sellers, it is reasonable to estimate that ARM paid at least somewhere in the low end of this range or slightly less. So the deal must have been for more than $20M.

    The future collaboration between the companies would seem to be focused on power management. Sonics has been investing in the development of advanced power management solutions that will leverage the NoC’s knowledge of interconnect traffic and SOC activity to more efficiently manage power domains. ARM’s collaboration with Sonics on this initiative seems to indicate that ARM believes that Sonics’ approach has merit. Given that ARM’s processors dominate the handheld marketplace power management is a huge issue. See the picture below to see a typical tablet SOC’s various power domains and how the NoC is well positioned to aid in managing power. If Sonics can use their relationship with ARM and their strength in NoC to bring about better power solutions for these devices this relationship will clearly deliver value to their mutual customers and position Sonics for significant growth in the years to come.


    DAC does not seem to be a place to meet with NoC companies, though Sonics is sponsoring the “Kickin’ it up in Austin” vents at DAC. However, Sonics is attending the Multicore Developers Conference this month if you’d like to meet them.

    Sonics, Inc. is the leader of system IP for cloud-scale SoCs. As a pioneer of network-on-chip (NoC) technology, Sonics offers SoC designers one of the world’s largest portfolios of system IP for mobile, digital entertainment, wireless and home networking. With a broad array of silicon-proven IP, Sonics helps designers eliminate memory bottlenecks associated with complex, high-speed SoC design, streamline and unify data flows and solve persistent network challenges in embedded systems with multiple cores. Sonics has more than 138 patent properties to date and has enabled its customers to ship more than two billion chips worldwide. Founded in 1996, Sonics is headquartered in Milpitas, Calif. with offices worldwide. For more information, please visit www.sonicsinc.com, www.sonicsinc.com/blog, and follow us on Twitter at http://twitter.com/sonicsinc.

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    A random walk down OS-VVM

    A random walk down OS-VVM
    by Don Dingee on 05-13-2013 at 11:14 am
    Categories: Aldec, EDA

    Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer wouldn’t try but a test engineer without a priori bias would.

    Continue reading “A random walk down OS-VVM”