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January 8, 2014

International CES: Day Four

International CES: Day Four
by Bill Jewell on 01-08-2014 at 7:00 pm
Categories: Uncategorized
1 Comment

Wednesday, January 8.

Sensors are big at CES. Big as in many vendors and applications, but small in size. Sensors were prominent features in automobiles, PCs, tablets and mobile phones. But the most exciting is the relatively new area of digital health and fitness. CES has 366 exhibitors in this category, with most of them featuring sensor technology.

In digital fitness, the LG Lifeband Touch won the Tech Radar Best of CES award for best fitness tech (pictured below). The sleek looking wristband flexes to fit your wrist with one end open, thus no pressure points. On its own it senses heart rate, motion, acceleration and altitude. Paired with an iPhone or Android phone it alerts to incoming calls or texts and controls music.

The best looking device was the Wellograph Sapphire Wellness Watch. The rectangular, moderate sized black watch has a sapphire crystal display and a choice of dress or sport band. It tracks pulse and activities and displays data and graphs. In contrast, some companies are still putting out bulky devices which look like you are wearing your phone on your wrist (as shown in the unidentified device below).

Wearable sensor devices which include health and fitness devices are expected to be a $1.8 billion market in 2014. Fitbit is the leader in fitness devices, claiming two-thirds of the market in 2013. This is certain to be a strong growth category in the next several years.

Headed home tonight. I will finish up with a summary of CES and what devices will have the most impact on the semiconductor industry in the next few years.

Low Power @ DesignCon 2014

Low Power @ DesignCon 2014
by Daniel Nenni on 01-08-2014 at 11:00 am
Categories: Ansys, Inc., EDA

Taking place annually in Silicon Valley, DesignCon is the premier educational conference and technology exhibition for electronic design engineers in the high speed communications and semiconductor communities.

Created by engineers for engineers, DesignCon is the largest gathering of chip, board and systems designers in the world and is focused on the pervasive nature of signal integrity at all levels of electronic design – chip, package, board and system. Combining technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest theories, methodologies, techniques, applications and demonstrations on PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test & measurement tools, parallel & memory interface design, ICs, semiconductor components and more.

DesignCon enables chip, board and systems designers, software developers and silicon manufacturers to grow their design expertise, learn about and see the latest advanced design technologies & tools from top vendors in the industry, and network with fellow engineers and design engineering experts.

The 2014 Technical Conference Program will consist of 14 tracks overing all aspects of electronic design, from chips through boards and systems.

Check out Who Attends DesignCon, and photos and videos from 2013!

Location
Date: Tuesday, January 28, 2014 – Friday, January 31, 2014
Location: Santa Clara, CA
EXPO– January 29 – 30, 2014
ANSYS Booth #513

Panel Sessions
System-Level Power Integrity: Tools Providers and Tool Users Engage
Date: Wednesday, January 29
Time: 3:45pm-5:00pm
Location: Ballroom G

Closing the Loop: What Do We Do When Measurements and Simulations Don’t Match?
Date: Thursday, January 30
Time: 3:45pm-5:00pm
Location: Ballroom H

Technical Papers
A Loewner-Matrix-Based Algorithm for State-Space Fitting of Frequency-Domain Data with Nonuniform Frequency Sampling
Date: Wednesday, January 29
Time: 10:15am-10:55am
Location: Ballroom K

Chip-Package-System ESD Simulation Methodology Using a Chip ESD Compact Model
Date: Thursday, January 30
Time: 2:00pm-2:40pm
Location: Ballroom J

Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs in the 20nm Technology
Date: Thursday, January 30
Time: 2:50pm-3:30pm
Location: Ballroom E

About Apache
The proliferation of high-performance mobile devices — such as smartphones and tablet computers — along with the trend toward smaller electronic systems are driving engineers to design and deliver more power-efficient products with extended battery life, while still satisfying increasing performance requirements. Meanwhile, rise in power consumption and electricity costs from the IT infrastructure required to support growing mobile connectivity demands more energy-efficient products. In addition, the explosion in system-to-system wireless communications is amplifying the amount of noise within and between ICs, threatening the system with malfunction or failure.

The Apache suite provides innovative power analysis and optimization solutions that enable engineers to design and deliver products meeting stringent power specification limits, while still reliably and consistently delivering power to the entire system and mitigating failures or performance degradation caused by power-induced noise. Apache’s comprehensive suite of integrated software and methodologies spans a full spectrum of power, noise and reliability solutions, including power reduction, power and signal integrity, thermal management, and EM, ESD and EMI verification, from early in the design phase through final system sign-off.

Apache’s differentiated platforms address the unique challenges associated with various phases of the IC and electronic system design process, including RTL-level power budgeting; IP power delivery integrity validation; SoC integration and power noise sign-off; and IC package/board power and signal integrity, reliability verification and cost optimization. Apache’s accurate and compact models enable RTL-to-silicon, analog-to-digital, and chip–package–system power methodologies that facilitate effective coordination among multiple engineering teams and help to drive the electronic ecosystem.

The combined Apache and ANSYS suite provides even more functionality. It enables R&D teams to solve chip power delivery problems, package/board thermal/electromagnetic extraction, system enclosures and time-domain circuit analysis. Multiphysics capabilities impart the ability to simulate various physical phenomena across chips, packages and systems, including power optimization, signal integrity, electrostatic discharge (ESD), electromagnetic interference/electromagnetic compatibility (EMI/EMC), heat transfer, fluid dynamics and structural mechanics. The multi-user aspect provides the simulation platform and collaboration tools that enable electronics, electrical and mechanical engineers — along with managers and executives from different divisions within the organization — to collaborate in designing increasingly complex products.

FD-SOI Memories

FD-SOI Memories
by Paul McLellan on 01-08-2014 at 11:00 am
Categories: FD-SOI, Foundries, STMicroelectronics

When people discuss capabilities of leading edge process nodes they tend to focus on digital logic. Microprocessors in particular. But a process requires more than just digital logic and standard cells to be successful. In particular, pretty much every SoC contains a lot of memory so the memory capabilities of a process are important.
Continue reading “FD-SOI Memories”

January 7, 2014

International CES: Day Three

International CES: Day Three
by Bill Jewell on 01-07-2014 at 10:45 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Tuesday, January 7

Today was the official start of International CES. The crowds were huge – almost every area of the massive Las Vegas Convention Center was crowded.

Now that we have all spent lots of money replacing our old picture tube television sets with big flat panel HDTVs, manufacturers are pushing the next big thing: Ultra High Definition (UHD) TV. Also known as 4K, UHD TV has about 8 million pixels compared to 2 million pixels in HDTV. The detail is incredible. The TV above is Samsung’s 105 inch diagonal, curved UHD TV. Samsung also showed a 110 inch flat UHD TV and an 85 inch bendable UHD TV which can move from flat to curved.

Size matters in UHD TV. Matching Samsung’s 110 inches were Chinese companies CNS and TCL. LG and Toshiba each had 105 inch UHD TVs in a 21 by 9 format, similar to a wide movie screen. Sharp measured in at 90 inches. Companies showing 85 inch UHD TVs included Panasonic, RCA, Sony and Chinese companies Changhong, Haier, Hisense, and Konka.

3D TVs which do not require glasses to view were shown by Haier, Konka, Samsung and Sharp. As with the Izon TV demonstrated on Monday, the glasses free 3D TVs did not have the intensity of 3D TVs which require glasses. However the 3D effect was very acceptable for casual viewing.

Tomorrow is my last day at CES, though the show runs through Friday.

Bill Jewell, www.sc-iq.com

More Articles by Bill Jewell…..

lang: en_US

January 7, 2014June 14, 2019

How to Optimize Analog IPs for High-end SoCs?

How to Optimize Analog IPs for High-end SoCs?
by Pawan Fangaria on 01-07-2014 at 12:00 pm
Categories: Cadence, EDA

Gone are the days when analog design had its sweet space on a single chip. However, it’s the main driver in this new electronic world which is geared by Internet-of-Things, wireless, mobile, remote control and so on. How does an electronic device sense a touch by human, motion, temperature, sound etc.? It’s the analog circuitry embedded into the SoC of your electronic device that connects the environment with the device. Quality, accuracy and speed of that sense matters very significantly, otherwise that electronic device will become a nuisance to you. Now you can very well imagine how complex and costly it would be to design a robust high-speed analog IP which can sit (without being disturbed by neighbouring noise) into the complex limited space, high performance, multiple functionality SoC of today. Typically, high performance data converters (between analog and digital), voltage regulators, sensors, clocks etc. are very common in demand.

The design can be better handled by looking at each issue objectively and focusing on important criteria to be met under particular circumstances. So, what are the key criteria to look at?

Sampling Rate – Faster sampling of data in a data converter achieves higher accuracy in rendition of analog signals. According to Nyquist theorem, to generate an accurate reproduction of an analog signal in digital form, the sampling rate should be higher than twice the highest frequency of the signal. However, there is cost involved in faster sampling; it requires higher bandwidth, more power consumption and challenge in synchronizing samples of each bit. Appropriate trade-off must be done depending on application area. The graph below summarizes typical levels of sampling rates and resolution for different applications.

Bit Resolution – This determines the accuracy of representation of analog signal into digital. A higher bit resolution produces analog signal more accurately into digital. A designer in this case can determine bit resolution based on how accurately a signal needs to be represented. For example, an audio device will need higher bit resolution as the voice needs clarity, whereas a thermal sensor in water temperature or air conditioner does not need that high resolution. The table below provides optimal ranges of sampling rate and resolution for various applications.

Noise Ratio – Noise reduces the accuracy of data conversion. Generally it is said that analog components are victims of digital aggressors in the semiconductor design. Care must be taken in placing the analog and digital components appropriately to keep SNR (Signal-to-Noise Ratio) under tolerable limits, even with possible margins by increasing bit resolution or sampling rate. Again, it depends on the type of appliance; an audio or wireless device is extremely sensitive to noise compared to a temperature sensor.

ENOB (Effective Number of Bits) – This reflects the actual performance of data conversion. Due to noise and distortion of signal, it’s not possible to get an ENOB as high as the number of bits in an ADC (analog-to-digital converter). An 11-bit ADC with an ENOB of 10.5 is considered to be well optimized and more effective design than a 12-bit ADC with an ENOB of 10. And hence it’s important that the system requirement are well understood before designing.

Power – This is a major concern for all designs, especially with analog circuits getting into mobile applications. It’s DAC (digital-to-analog converter) that needs more power to drive higher amplitude signal. The challenge is to achieve high amplitude without sacrificing power.

While considering all these challenges and the need for careful evaluation of options, what we did not talk about is the time taken to design such analog IPs. It takes considerable time and that adds into overall design cycle time impacting on time-to-market in a highly competitive semiconductor industry. It’s highly desirable to choose best IPs already optimized with performance and standardized on different criteria and integrate them into SoCs. Cadence offers a broad portfolio of more than 250 silicon-proven analog IPs that include 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC and 12-bit 2GSPS dual DAC which support 28nm designs and provide a conversion rate up to 10X faster compared to competing solutions.

Bob Salem and Kevin Yee from Cadence have very elaborately described these challenges of high-speed analog IPs in their whitepaperposted at Cadence website. It’s an interesting read.

International CES: Day Two

International CES: Day Two
by Bill Jewell on 01-06-2014 at 8:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Monday, January 6, 2014.Press conference day at International CES, starting with LG at 8 am and finishing with Sony at 5 pm. Some of the most interesting presentations (I will not overuse the word “cool” today) were:

Izon, LLC introduced a glasses-free 3D TV. They demonstrated on a 24 inch screen playing the latest “Superman” movie from a 3D Blu-ray player (they promised bigger screens at their booth). The display was definitely 3D, but not quite as pronounced as with 3D glasses.

Intel introduced RealSense technology designed make human interaction with technology more natural, intuitive and immersive. The first product is a 3D camera built into PCs and tablets which allows accurate recognition of gestures and facial features. Intel demonstrated games, educational applications, music and video conferencing all controlled by gestures without touching the PC, keyboard or mouse. Intel also introduced the next-generation Dragon Assistant from Nuance which it calls a conversational personal assistant. Will this finally be the voice recognition technology which works well enough for people to begin talking to their PCs (instead of swearing at them)? Stay tuned.

International CES: Day One

The most exciting press conference of the day was Qualcomm’s unveiling of the first electric formula 1 style race car. The Spark-Renault SRT_01E will run in a series of races called the FIA Formula E Championship beginning in September 2014 in Beijing, China. Qualcomm is a major sponsor and is using the Formula E to promote its push into automotive communications applications. The car can accelerate from 0 to 62 mph in 2.9 seconds and has a top speed of about 150 mph. When the car was making laps the most noticeable sound was squealing tires rather than engine noise.

Tomorrow is the official start of International CES.

Bill Jewell, www.sc-iq.com

A Brief History of Andes Technology

A Brief History of Andes Technology
by Paul McLellan on 01-06-2014 at 4:47 pm
Categories: Andes Technology, IP

I like to call Andes Technology the biggest microprocessor IP company you’ve never heard of. I wrote about themback in October when I sat down with them during the Linley Microprocessor Conference. Part of the reason you have never heard of them is that they are based in Taiwan and most of their business is in Taiwan and China. Mediatek is a big customer. As I said in the above blog, their strategy is partially not to be ARM, to be the processor that you can put where the code is not visible to the end user (inside a WiFi chip, for example). There is no compelling reason to use an ARM there and Andes reckon their cores deliver more performance for both area and power than equivalent ARMs. I’m sure Andes is more cost-effective than an ARM license too.

As I said above:”So what sort of performance do they deliver? With a standard 40LP TSMC library (so not even in 28um) the N1337 delivers 908 MHz and 79 uW/MHz in 0.25mm2, which is 50% higher performance at 1/3 lower power and slightly smaller area than their competition. With a speed optimized library it exceeds the gigahertz barrier (still in 40LP).”

I said in October that Andes had just closed their first US licensee. Now they have several. So you can expect to hear more about them as their US footprint grows. They also closed their first Japanese licensee last summer. I’ll have to find a new name for them once everyone has heard about them, I guess.

The big opportunity is the Internet of Things (IoT) where most of the devices will not be user-programmable so it is a level playing field as to which microprocessor it makes sense to use (unlike in the application processor in a smartphone where the instruction set shows through to all the Apps developers and even someone as established as MIPS doesn’t have traction). On a level playing field, technical specs like power, performance, area, cost all become more important and the instruction set architecture less so.

Andes was founded in 2005 in Hsinchu Science Park (near TSMC). They have over 100 employees located in Taiwan, China, Korea, Japan and US.

They already have around 80 licensees, and over 60 partners for things like compilers, debuggers and other aspects of a processor ecosystem. Over 6000 people use the AndeSight software development tools. Last October they had shipped over 300M processors. Or rather their licensees had shipped over 300M chips containing Andes processors. Their product line has at least 6 cores in, ranging from N7 and N8 which have simple 3 stage pipelines, all the way up to the N12 and N13 that have 8 stage pipelines.

Find out more on the Andes Technology website here.

GlobalFoundries Has a New CEO

GlobalFoundries Has a New CEO
by Paul McLellan on 01-06-2014 at 4:07 pm
Categories: Foundries, GlobalFoundries

Sanjay Jha is taking over as CEO of GlobalFoundries. His background is in mobile. He was at Qualcomm in the early part of his career and was COO from 2006 to 2008 before going to be co-CEO of Motorola and then, when the company was split, CEO of Motorola Mobility. That was acquired by Google and he stepped down after the acquisition closed.

He was born in India. His educational background is a little odd, with an engineering degree from University of Liverpool (in England) and a PhD in EE from University of Strathclyde (in Scotland, and where I actually worked for 4 months between my undergraduate degree and my own PhD, as it happens).

Ajit Manocha was always officially acting CEO, a safe pair of hands while a new CEO was found. He will return to his role as an advisor to the company’s shareholder (Abu Dhabi’s Advanced Technology Investment Corporation, ATIC). GlobalFoundries only has one shareholder. They used to have 2 but ATIC bought out AMD’s share in 2012.

GlobalFoundries also announced (actually last Friday) that they will deploy an additional $9-10B of capital over the next couple of years, primarily the buildout of Fab 8 which is in Saratoga New York, and is GlobalFoundries’ most advanced fab. Some will also be invested in Dresden Germany and in the ex-Chartered fabs in Singapore.

GlobalFoundries is the second biggest foundry, but it is a long way behind TSMC both in terms of revenue and in its capability to deliver leading edge processes so Sanjay certainly has plenty of challenges. But the brass ring in the leading edge foundry business is the mobile industry and his connections there from Qualcomm and Motorola have to be an advantage. The biggest challenge is really to turn what seem to be almost unlimited amounts of money from ATIC into a business that is truly competitive with TSMC, Samsung (and maybe Intel). The other foundries such as UMC and SMIC seem to be struggling even more than GlobalFoundries (or are specialized analog fabs that don’t really compete in the same business). In the long run, if GlobalFoundries is going to be truly successful at the leading edge it needs to get some business from the likes of Apple, Broadcom, nVidia and…err…Qualcomm. He might be able to get them to return his phone calls having been COO.

I wish him luck. The foundry ecosystem needs a strong number 2 competitor.

India Spearheading into Space Technology

India Spearheading into Space Technology
by Pawan Fangaria on 01-06-2014 at 11:00 am
Categories: General

Success follows failures, if your perseverance in high enough to achieve any kind of arduous goal. This adage was witnessed by Indian Space Research Organization (ISRO) successfully launching India’s first rocket, Geosynchronous Satellite Launch Vehicle GSLV D5 which carried GSAT 14 advanced communications satellite and successfully placed it in the orbit. Earlier two attempts had failed – one in last August was aborted before launching due to fuel leak from one of the rocket’s engines and the other in December 2010 (which employed Russian cryogenic engines) burst just after take-off. This exemplary success puts India into the small group of elite nations having this technology. As of date, only U.S., Japan, France, European Space Agency, China and Russia had this technology. By ushering into such advanced technology in global arena, Indian scientists bring unprecedented pride for India.

The GSLV D5 was indigenously developed in India by ISRO under its ambitious space programme. There was a need felt to put heavy satellites into higher orbits above 35000 KM from the Earth. India had been trying since long to develop its own cryogenic engines because a cryogenic rocket can provide higher thrust per kilogram of propellant. However cryogenic technology is extremely complex because of its propellants (liquid oxygen and liquid hydrogen) which require extremely low temperatures; liquid hydrogen at below -250 degree centigrade and liquid oxygen at below -150 degree centigrade. This further involves thermal and structural issues of the engine. The rocket itself weighed about 415 tonnes and the GSAT 14 satellite, which it carried, weighed about 2 tonnes. The launch was done from the Satish Dhawan Space Centre at Sriharikota in Andhra Pradesh state of India on Sunday, 5[SUP]th[/SUP] Jan.

Dr. K. Radhakrishnan, Chairman of ISRO is extremely proud of this accomplishment by his ‘Team ISRO’. On the momentous day he said, “Team ISRO and project directors put their heart and soul in making this proud moment for the country.” Including last 3-4 years of rigorous exercise, it took overall about 20 years to develop this proven cryogenic technology in the country. This makes India self-reliant in deploying its communication satellites into space; so far the rocket from France (Ariane) was being used to launch communication satellites in geostationary transfer orbits. The GSAT 14 satellite will be used for telecommunication and telemedicine applications.

This technology is expected to provide large push to Indian economy by saving foreign exchange for launching home satellites and at the same time earning large foreign cash for launching satellites of other countries in this lucrative global business, thus stabilizing the CAD (Current Account Deficit) situation in India. Today, in the international market, launching charge for a satellite is approximately 80 to 90 million USD. And demand for communication infrastructure is ever growing globally.

It’s a great feat for India which is struggling to balance its imports against exports. For that reason the India Government has been pursuing for two semiconductor foundries also in India, so that the chip manufacturing can be done here itself and not imported for its domestic demand. Let’s see how the future unfolds for India with this kind of technological thrust.

Imagination’s New GPU Cores

Imagination’s New GPU Cores
by Paul McLellan on 01-06-2014 at 9:00 am
Categories: Imagination Technologies, IP

This morning Imagination announced their latest GPU cores, including the world’s smallest fully-featured OpenGL ES3.0/OpenCL GPU core. More on that below. And it is the Internet…and graphics…so cats. Graphically rendered cats.

The first core is a a high end core new generation PowerVR Series6XT architecture delivers up to 50% higher performance and advanced power management. The Series6XT architecture features market-leading scalability, supporting implementations up to eight compute clusters that scale linearly in GFLOPS and texturing rates. With OpenGL ES 3.0 support across the range, Series6XT provides among the highest performance OpenGL ES 3.0 GPUs in the industry. Today they unveiled the first three cores in the Series6XT generation with two, four and six compute clusters respectively.

The PowerVR series is already the market leader, at least according to John Peddie research. There are now over 45,000 developers working on graphics applications using this portfolio of IP.

Here is how the whole family fits together for everyone who wants to see the whole (announced) roadmap:

This achieves up to 50% performance increase on the latest industry benchmarks compared to their previous generation of cores, with both the best performance in terms of GFLOPS/mm[SUP]2[/SUP] and GFLOPS/mW. There are architectural enhancements such as streamlined instruction set for improved application performance, the next generation of the hierarchical scheduling technology (HST) for higher resource utilization, sustained polygon throughput and improved pixel fillrate along with other improvements for better parallel processing.

The PowerGearing tile-based deferred rendering (TBDR) is the world’s most efficient. This enables fine-grained control of all GPU resources and dynamic demand-based scheduling, routing power only to needed resources to get the best in low-power performance.

The PVR3C triple compression provides for lossy texture compression (down to around 1 bit per pixel), but lossless image compression (about 2X) and lossless geometry compression. This reduces bandwidth requirements and thus leads to lower power.

The lower-end new Rogue GPUs are targeted at entry-level segments ideal for applications with limited area and bandwidth where the higher powered cores are inappropriate. There are four cores in the family:

PowerVR Series6XE G6050: takes advantage of the latest Rogue architectural developments and extends the scalability beyond one cluster to a half-cluster while maintaining full software compatibility, creating the smallest fully-featured OpenGL ES3.0 and OpenCL-capable GPU core available
PowerVR Series6XE G6060: This core augments the half-cluster design of the G6050 with the addition of second generation lossless image compression (PVRIC2), providing an optimal balance of small size and bandwidth reduction for products such as entry-level mobile products, tablets and full HDTVs and set-top boxes.
PowerVR Series6XE G6100: an updated and further optimized version of the original core and features a single Unified Shader Cluster (USC) combined with a high-performance texture mapping unit, enabling it to deliver the same raw fillrates as multi-processor GPUs from the previous generation.
PowerVR Series6XE G6110: single-cluster core extends the above G6100 design, adding PVRIC2 for improved throughput, reduced bandwidth, conserved power and improved system performance—key for products such as low-cost 4K UltraHD TVs and tablets where bandwidth is a limited, valuable resource.

Both cores come with physical design optimization kits (DOKs) to optimize power, performance and area (PPA). These include reference flows, tuned libraries from partners, characterization data and more.

More details on Imagination’s website here.