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Intel Bay Trail Fail

Intel Bay Trail Fail
by Daniel Nenni on 09-15-2013 at 5:00 pm
Categories: Foundries, Intel Foundry, TSMC

Now that the IDF 2013 euphoria is fading I would like to play devil’s advocate and make a case for why Intel is still not ready to compete in the mobile market. It was very clear from the keynotes that Intel is a chip company, always has been, always will be, and that will not get them the market share they need to be relevant in mobile electronics, just my devil’s advocate opinion of course.

The first argument is the Bay Trail tablet offerings which are mediocre at best. The WinSuperSite has a nice Fall Tablet Preview with pictures and everything you need to know to decide NOT to buy one. Notice there are no Bay Trail smartphones, just tablets big and small. How many people or corporations buy the same brand tablet and phone? How many people or corporations will buy a new tablet every two years like they do smartphones? I still have my iPad2, and, like my laptop, I have no plans to replace it until I absolutely have to (3-5 years). My bet is that there will be a fire sale on Bay Trail devices next year so wait until then if you really want one.

“You’ve got to start with the customer experience and work backwards to the technology.”

The second argument is the Apple 64 bit SoC announcement last week which totally eclipsed the Intel Bay Trail hype, absolutely. Why is 64 bit a big deal? The additional performance is what everybody is talking about but the real reason for 64 bits is software portability. Corporate America can now move PC based applications to Apple tablets/phones which will further accelerate the decline of Intel’s PC revenue stream. The other thing to note is that Apple is moving away from buying chips, instead they create their own custom SoCs based on a licensed ARM architecture. This allows Apple to optimize the SoC for iOS and deliver the optimum customer experience. Qualcomm and Samsung also create custom SoCs and, between the three companies, they own the mobile market. So who is Intel going to sell chips to? Certainly not the sub $50 phone makers in emerging markets. Microsoft and the legacy PC manufacturers is all that is left?

The third argument is: Do you really care what chips are inside your phone? Thanks to Intel marketing it is clearly marked that my laptop is powered by an Intel i7. For tablets and smartphones that is not the case nor will it ever be. The only reason why I know my iPhone 5 has a 32nm dual core SoC is because I work with the foundries, which is why I also know that the iPhone5s A7 SoC is a 28nm LP quad core SoC manufactured by Samsung. For those of you who think it is 28nm or 20nm silicon from TSMC you didn’t read my “TSMC Apple Rumors Debunked”. The iProduct 6 will have TSMC 20nm silicon and the iProduct 6s will be both Samsung and TSMC 14nm, my prediction.

Fourth is Intel leadership. I met the new Intel CEO Brian Krzanich (briefly) after his keynote on Tuesday. The keynote itself was good. Not too polished, sometimes they look like something out of Las Vegas. Brian is definitely an engineer and even added a Q&A session afterwards which was new. The answers to the questions however confirmed that Intel is still Intel. Will Intel deliver synthesizable cores? No. Will Intel license their IP? No. Will Intel allow their IP to be manufactured by anyone else? No. Will Intel start with the customer experience and work backwards to the technology? Absolutely not. Intel thinks they will dominate mobile electronics like they did the PC with old school benchmarking. Unfortunately, Samsung, ARM, Apple, Qualcom, Broadcom, Mediatek, Nvidia, TSMC, and the rest of the fabless semiconductor ecosystem will not allow that to happen, no way, no how.

Also read:

The Significance of Apple’s 64 Bit A7

Intel Quark: Synthesizable Core But You Can’t Have It

lang: en_US

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Semiconductor Manufacturing in India?

Semiconductor Manufacturing in India?
by Pawan Fangaria on 09-15-2013 at 11:30 am
Categories: Foundries


Last week I heard about the Indian Cabinet approving the proposal for setting up of two Fabs in India. One led by IBM, Tower Jazzand JP Associates(an Indian business house), and the other led by HSMC(Hindustan Semiconductor Manufacturing Co.), ST Microelectronicsand Silterra. Indian Semiconductor community including IESA (India Electronics and Semiconductor Association) has welcomed the step; indeed it must, naturally, as the community has dreamed since long about having a Fab in the country. I am specifically delighted to hear this as I get a nostalgic feeling after remembering about the 3 micron Fab during my first job at ITI (Indian Telephone Industries in those days), Bangalore in 1990s. That became obsolete long ago; also another one at SCL (Semiconductor Complex Limited at Chandigarh near Delhi) became dysfunctional. Since then any Fab has not seen the light of the day in India so far.

It’s definitely something to cheer about (as this can aid in containing a significant portion of the estimated $400B electronics revenue by 2020 within India, thereby cutting the Current Account Deficit, year over year) provided it comes up to be true in a sustainable business sense which means several things; I am going to talk about in a minute. But before that I must say that it can be sustainable only when it is able to create Net Positive Value (yes essentially positive net present value and economic value addition) for the country as well as for the world. So, what are those factors which need to be looked at and questions answered before we can celebrate the success?

A Long Term Plan – As Foundry setup is highly Capital intensive, it must be supported with a solid long term plan and financial backing. I am sure, before proposing they must have planned for this; my concern is only that the tri-party – the Government, the Indian private partner and the MNC partner firmly support the plan for say, 10 years at least. What-if scenario needs to be analyzed and firmed up sooner than later. The whole contingency plan needs to be in place now for the initiative to last forever.

Fiscal Sustenance – This specifically pertains to the Indian Government. As tax holiday, subsidy, zero duty, financial investment etc. will play an important role in promoting the Fab along with the semiconductor industry in India; this will put further pressure on already large Fiscal Deficit. How much prepared is the Government to support this?

Support Infrastructure – This is a very important aspect which needs to be looked at for smooth running of the Fab. Can a world class, sustainable infrastructure, as required by a modern Fab be provided? Say swift transportation, large quantity of pure water, uninterrupted electricity, communication, pollutant free environment etc. I am sure, these can be done, but that needs careful planning, not only within the Fab but outside as well for an effective operation which can provide positive end result.

Government Policy – This is one of the most important factors for such a massive step to be taken. The policy (that includes all kinds of subsidies, which may be tapered down in future with due conditional clauses) taken up now must be valid and stable for at least 10 to 15 years irrespective of which party is in power.

Business Leadership – When I talk about sustenance, business leadership by this consortium is a must, which is the core which emanates from the owners of the organization. They need to own the business as one entity. They need to provide the whole chip solution and not parts of it. The next comes operations, the foundry must produce at profitable cost (infrastructure and environment plays an important part in it) to remain viable. Otherwise, import of chips or its parts will continue at lower cost and the capacity of the foundry will remain idle. We have seen examples in other areas like capital goods and some commodities imports in India. Also, the foundry needs to produce what the market demands. Another aspect of business leadership – It needs to integrate with the world market in this modern globalized world, collaboration in the semiconductor ecosystem is a given.


Technology Leadership – Although I have no information about the process nodes and the like, I must say that in order to remain in business, the technology must be forward looking, otherwise it may become obsolete without giving any notice in this fast changing technological environment and we may go back to square one. Another aspect of technology leadership is that it must be superior and look up to the world market rather than only looking at Indian domestic consumption and cutting down on electronics import. That short sightedness can again lead to obsoleteness in due course of time.

India has been a service oriented market. It needs to transform itself into product oriented market. And for that there is lot more which needs to be done by the Government, by business leaders, entrepreneurs and the people in general, to change the mindset to take up ownership. It needs a positive vibrant environment where people and specifically entrepreneurs are able to see the real value created by their suppliers and employees, and reward them, and in return create greater value for themselves. It must be a win-win situation.

Let’s see where we go from here on realization of Foundry business in India. Comments welcome!

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Sidense and TSMC Processes

Sidense and TSMC Processes
by Paul McLellan on 09-14-2013 at 2:21 pm
Categories: IP, Sidense, TSMC

I’ve written before about the basic capabilities of Sidense’s single transistor one-time programmable memory products (1T-OTP). Just to summarize, it is an anti-fuse device that works by permanently rupturing the gate oxide under the bit-cells storage transistor, something that is obviously irreversible. Also, compared to devices that depend on sensing the presence or absence of a charge the read voltages are low and so the memory is naturally low power. The memory does require some non-standard voltages, especially for programming, but these are all internally generated by charge pumps. Another key advantage of the anitfuse approach is that it can be manufactured in a standard digital process with no additional masks or process steps required.

Sidense will be presenting at TSMC’s OIP on October 1st. The technology has been proven in both poly gate and HKMG gate-last. As a result there is broad support for TSMC processes from 40nm down to 20nm (all planar) with FinFET support currently in development. Sidense 1T-OTP has completed IP9000 assessment across many nodes with more coming later this year and next year.

Obviously the picture at the start of this article is a planar process and in FinFET the gate-oxide is around the fin. Nevertheless, the FinFET structures align well with Sidense’s OTP implementation. Compared to 20nm, the 16nm FinFET implementation has the same bit-cell architecture and OTP design, although the bit-cell and macros are smaller, with lower leakage and better performance.

There are also other Sidense products suitable for use in other TSMC processes typically used for analog, mixed-signal, high voltage etc. However, the Sidense memories only depend on the underlying standard digital process.

Betina Hold, director of R&D at Sidense, will be presenting An Antifuse-based Non-Volatile Memory for Advanced Process Nodes and FinFET Technologies at 4.30pm on the IP track (in the unenviable slot between attendees and beer). Register for OIP here. More details on Sidense’s product line here.

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Back To The Future: 50th Anniversary of EDA

Back To The Future: 50th Anniversary of EDA
by Paul McLellan on 09-12-2013 at 1:03 pm
Categories: Uncategorized
3 Comments

October 16[SUP]th[/SUP] at the Computer History Museum, EDAC is hosting EDA: Back to the Future to celebrate 50 years of EDA. EDAC always has a fall event of some sort and historically it has been the Kaufman Award Dinner. This year, the Kaufman Award was presented (to Chenming Hu) at 50[SUP]th[/SUP] DAC, so the fall EDAC calendar was open. Since Calma was founded in November 1963, which seems near enough to count as the beginning of EDA, EDAC decided to throw a big party – an industry reunion of sorts – to celebrate EDA’s 50[SUP]th[/SUP] Anniversary.

One purpose of this event is to raise money for the Computer History Museum’s EDA Oral Histories Collection and Exhibit, a project (driven by Doug Fairbairn) to capture and preserve the history of EDA.

I talked to Kathryn Kranen (chief EDAC honcho. Or would that be honcha?) and she said that the goals were:

  • Bring together the EDA community, past and present
  • Create a fun, highly entertaining evening, with good food and wine
  • Raise money for the cause: capturing and preserving EDA history

The museum will be open privately for us that evening. If you have not seen it since the remodel then I highly recommend it. There will be 1½ hours to mingle (with good wine!) before the banquet dinner and entertainment begins.

At dinner, each table will be “hosted” by an industry luminary. You might sit with a previous Kaufman Award recipient like Bob Brayton or Randy Bryant. Or maybe one of the founders of EDAC, Rick Carlson or Dave Millman. Perhaps a previous CEO like Jack Harding, Penny Herscher, Bernie Aronson, Rajeev Madhavan, or Sanjay Srivastava. One of the current EDAC board members: Aart de Geus, Lip-bu Tan, Wally Rhines, Simon Segars, John Kibarian, Kathryn Kranen, Ravi Subramanian, Dean Drako, Ed Cheng, or Raul Camposano. Or an investor who has focused on EDA, like Jim Hogan or John Sanguinetti.

During dinner, Bill Joyner will reprise his history of EDA from its beginnings to the future, that everyone loved at DAC but that many people (including me) missed. Later there will be the live auction complete with comedian auctioneer. So if you want to purchase lunch with Aart, a cocktail party with Kathryn, or a time-slot to pitch to an EDA-friendly VC, this might be the evening for you. Of course, there will be the more traditional auction items like luxury time-shares, a private sailing outing, professional golf lessons, a collection of wine, and restaurant gift certificates.

If you want to donate something to the auction, then contact Mike Gianfagna. If you want to donate an original workstation from early days of EDA, then contact Doug Fairbairn (and you will also qualify for free admission to the event).

Buy tickets here.


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Analog Characterization Environment (ACE)

Analog Characterization Environment (ACE)
by Daniel Nenni on 09-12-2013 at 10:00 am
Categories: EDA, TSMC

I’m looking forward to the 2013 TSMC Open Innovation Platform Ecosystem Forum to be held Oct. 1[SUP]st[/SUP] in San Jose. One paper in particular that has my attention is titled, “An Efficient and Accurate Sign-Off Simulation Methodology for High-Performance CMOS Image Sensors,” by Berkeley Design Automation & Forza Silicon. It is not every day that we get a chance to learn how design teams are tackling the tough verification challenges in complex high-performance applications, such as image sensors.


CMOS Image Sensor

The paper will discuss how many image sensor performance-limiting factors appear only when all of the active and passive devices in the array are modeled, including random device noise and layout parasitics. Coupled with the highly sensitive nature of image sensors, where tens of microvolts of noise can create noticeable image artifacts, these characteristics create an enormous challenge for analog simulation tools, pushing both the accuracy and capacity simultaneously.

The presentation will highlight image sensor design and verification and include a description of Forza’s verification methodology, which uses a hierarchy of models for the image sensor blocks. At higher levels of the hierarchy, the complexity of the model is reduced, but the accuracy of the global interactions between blocks is maintained as much as possible.

CMOS Image Sensor Block Diagram

Forza’s verification flow relies on the Berkeley Design Automation (BDA) Analog FastSPICE (AFS) Platform. AFS is qualified on the latest TSMC Custom Design Reference Flow and, according to Forza, has significantly improved their verification flow.

Results will highlight how the AFS Full-Spectrum Device Noise, included in the latest TSMC Custom Design Reference Flow, validates that the sensitive ADCs and readout chain will withstand the impact of device noise and parasitics. For top-level sign-off, AFS AMS enables Forza to speed up verification by using Verilog to model non accuracy-critical circuits while maintaining nanometer SPICE accuracy on blocks that were independently verified in other tools. AFS Mega has the required capacity, speed, and accuracy required for us to perform verification of over 700 signal chains at the transistor level, including extracted parasitics.


ACE Visual Distribution Analyzer – 1000 Iterations

In terms of characterization, Forza relied on BDA’s Analog Characterization Environment (ACE) to improve their characterization coverage and efficiency. Results include Monte Carlo-based analysis to predict image sensor nonuniformity due to device mismatch. Additionally, the AFS Circuit-Specific Corners, included in the latest TSMC Custom Design Reference Flow, efficiently eliminates the limitations of traditional digital process corners and generates circuit-specific corners for each measurement suitable for analog designs.

Evaluation

Datasheet

TSMC OIP

Also read: BDA Introduces High-Productivity Analog Characterization Environment (ACE)

lang: en_US

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The Significance of Apple’s 64 Bit A7

The Significance of Apple’s 64 Bit A7
by Ed McKernan on 09-11-2013 at 9:00 pm
Categories: General

The disappointment amongst analysts is palpable. Dreams of low cost iphones for the masses were kicked away when Apple introduced their two new iphones at the same price points as the old ones. Clearly Apple is playing a different game than what most others are anticipating as the market runs to 5BU. The market has split into the land of free Android hardware and software (80% of the market) and that of the 20% profitable niche that has led Microsoft to buy Nokia in order to save the “burning platform.” The truth is every platform is on fire as the big ecosystem players try to profitably leap frog to where the dollars are. Tim Cook has never explicitly said so, but his goal is not to offer cheap iphones to the masses, rather it is to conquer the Corporate Wintel Empire in as short a period of time as possible. The refreshed iphones will support his efforts, however it is possible that A7 powered iPADs will be a more significant contributor.

Microsoft’s acquisition of Nokia’s phone business is an affirmation that in the end software must reside on a physical device and at the reach of every finger-tip. Microsoft and Intel had 30 years to refine, improve and cost reduce the PC thereby displacing all but the fewest of mainframes. They were even able to execute a mid life kicker with mobile PCs. However, in the end, cellular changed the formfactor requirements thus sending PCs to the legacy farm. The folks in Redmond see where the thread of a reduced corporate compute footprint combined with lack of control of today’s mobile leads. And yet, with as profitable Office is, they refuse to port to iOS because the hardware guys are now in control.

Apple’s introduction of the 64-bit A7 CPU with a “desktop class architecture” and over 1Billion transistors and 2X performance is messaging straight out of the Intel PR handbook. The bar has been raised and they will now start the corporate spec-manship game against their rivals. Add in the security message of iOS and we have the transmorphing of the messages that Wintel used to sell the corporate world to those that Apple will use.

Beyond the messaging, one has to think of the impact a 64 bit A7 will have across an entire platform of products. While the new CPU is at this stage overkill for the iphone, it is certainly interesting in what it could bring to the iPAD or an ARM based Mac Air. On the roadmap must surely be a multitasking iOS that requires increased CPU horsepower and the ability to address more than 4GB of memory. Apple has entered x86 Silvermont territory.

The cannibalization of the 9.7” iPAD by the iPAD mini this past year shows not only are there multiple tablet market segments but that a sustainable high end market requires more than just a larger screen. The consumer would rather surf the internet with a smaller, lighter tablet and skip the keyboard. Apple has been slow to upgrade the larger iPAD into something meaningful and perhaps it is all because they were waiting on the A7 to power a mobile that can truly offer “Office functionality.” Look for VmWare and Parallels as well as iwork to be leveraged to offload Microsoft wherever possible. As for the A7, the 102mm die size is quite interesting as it is around the same point where Intel in the 1990s would build their low end CPU targeting corporate. It is obviously an economic, wafer yielding inflection point.

It is safe to say at this point that no one in the PC or mobile industry can accurately predict the true size of the PC and tablet markets given the turnover of new products, the absorption of new technology and the inability of buyers to fully understand the productivity tradeoffs. Experimentatin leads the way which means Apple, Microsoft, Google and the rest of the players will be introducing even more products at every smaller price point divergences in order to stay close to changes in trends.

History says that consolidation follows.

With its expensive iphone 5C and 5S swimming in a sea of <$100 smartphones, Apple seems to be drawing a line in the sand in the consumer space while it builds its moat around corporate. The winner of corporate though has to win the $500-$999 mobile space and that is up for grabs. The mobile has to be very light, outfitted with a 10-11” screen and keyboard and last all day on a charge. Apple has it in the MAC Air, but it is $999 and above. The PC players are rushing in with Windows and Android tablets. Depending on what Apple introduces in the next couple months will determine if they see a return to growth in this segment or if the battle ends up raging for years.

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Emerging Trend – Choose DRAM as per Your Design Need

Emerging Trend – Choose DRAM as per Your Design Need
by Pawan Fangaria on 09-11-2013 at 7:00 pm
Categories: Cadence, EDA

Lately I was studying about new innovations in memory world such as ReRAM and Memristor. As DRAM (although it has become a commodity) has found its extensive use in mobile, PC, tablet and so on, that was an inclination too to know more about. While reviewing Cadence’s offering in memory subsystems, I came across this whitepaperwhich provides a comprehensive description about some of the existing and some of the upcoming (in production) DRAM interfaces along with their Pros & Cons.

Obviously, due to price pressure, DRAM business is a volume game and there is not much scope of differentiation. However, amid increasing SoC size, architecture and complexity, and more importantly mobile market driving DRAM business, it’s worth paying attention to the important demand of increased bandwidth, operating frequency and low power consumption. In view of these demands, different architectures of DRAM interfaces are emerging. Let’s take a brief look at these here, but one must see the whitepaper to know more about the actual details and also the references to those such as JEDECand HMC.

[LPDDR3 Architecture]

LPDDR3 (Low-Power Double Data Rate 3) – This interface suits well for mobile devices which require high memory density and performance and low power consumption. This also has lower I/O capacitance which helps in achieving increased bandwidth and operating frequency.

[LPDDR4 Architecture]

LPDDR4 – This is the latest standard from JEDEC, optimized for next generation mobile devices. This will provide double the bandwidth of LPDDR3 at similar power and area. It has lower page size, multiple channels and reduced command/address bus pin count. This will be in mass production in 2014.

[Wide I/O 2 Architecture]

Wide I/O 2 – This is again from JEDEC, expected to reach mass production in 2015. This supports 3D-IC packaging for PC and server applications and can be used for high-end mobile applications. It covers high-bandwidth 2.5D silicon interposer and 3D stacked die packaging for memory devices. In this architecture, designers can use EDA tools to take advantage of redundancy at the logic level to minimize device failures. Cadence Encounter Digital Implementation allows designers to route multiple redistribution layers (RDL) into a microbump or to use combination bumps. If one bump falls, the remaining bumps can carry on normal operations.

In 2.5D staking, cooling is not much of a problem. However, in 3D staking heat dissipation from the middle of the stack could become a problem and hence needs careful thermal planning.

[HMC Architecture]

HMC (Hybrid Memory Cube) – This is being developed by Hybrid Memory Cube Consortium and supported by many semiconductor and technology companies. It combines high-speed logic process technology with a stack of TSV (Through-Silicon-Via) bonded memory die. This architecture allows more DRAM I/O pins and hence provides the highest bandwidth among all architectures (as high as 400G). In comparison to LPDDR3, a single HMC can provide 15X higher performance and consume 70% less energy per bit. However, the cost of this technology is also high.

[HBM Architecture]

HBM (High Bandwidth Memory) – This is an emerging standard for graphics, defined by JEDEC (JEDEC’s HBM task force is now part of JC-42.3 sub-committee), expected to be published by late 2013. It’s expected to be in mass production in 2015. It’s stacked DRAM die using TSV technologies to support bandwidth from 128GB/s to 256GB/s.

So which memory standard works best for your design? There is no definitive answer. It really depends on the requirements of the application for power, performance and area. And not to forget, price to pay. For example, LPDDR4 should be good enough for budget mobile market, whereas computer graphics with high resolution may require HBM.

It will be worthwhile to look at the Cadence whitepaperwhich has detailed analysis of these architectures and the information about what Cadence provides in support of these architectures, such as memory controller and PHY IP. It also provides Cadence’s roadmap to offer support for upcoming DRAM architectures. Cadence also provides memory model verification IP to verify memory interfaces and ensure design correctness.

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Breaking news: Microsoft acquires Apple!

Breaking news: Microsoft acquires Apple!
by Eric Esteve on 09-11-2013 at 4:51 am
Categories: General

Despite the relative success of their latest smartphone, iPhone15s, the Cupertino firm had never been able to renew with the success of legendary iPhone5s, launched ten years ago, in 2011. As of today, we don’t know if Microsoft will keep iPhone and iPad product lines, or decide to provide these with a lethal injection…

Some history: back in 2011, Apple (iOS) was enjoying 50%+ market share in some of the highly developed countries, like 79% in Japan or 50% in Sweden, and was still beating Android (by 1%) in the US…

If we look at Apple historical results, the company has already experienced such a market share decline, and seen sales decreasing on a booming market: it was in 1995, the product was the Macintosh. Apple’s board decision to fire Steve Jobs a while ago (1985) and to replace him with beans counter was clearly the reason explaining such a decline:

Steve’s come back in 1997 has helped the company to return to success, with the iPod launch in 2001, quickly generating huge sales and profit. Surfing on this success, Apple successfully launches a revolutionary smartphone in 2007… Even if the smartphone concept had been invented by IBM with the “Simon Personal Communicator” in 1992, and hit success with the Nokia 9000 in 1996, and later with the “Blackberry” from RIM, launched in 1999, the iPhone launch in 2007 had completely change the consumer perception, at the point that such an expansive device, supposedly reserved to a business elite, has penetrated even house (I should say every room, as kids used it as well). So, Apple could have said a big “Thanks” to Steve Jobs, who has moved in less than ten years a quasi-bankrupt company into… Wall Street largest valued company! But this was in 2012, and the Cupertino firm has duplicated, in the meantime, the former MAC story, like highlighted by this picture (in fact, just replace “Word Perfect”, the MAC OS text editor in blue by MAC, and “Word” in red by PC or Windows).

The “Word Perfect” curve is just representing that has happened to “iOS” twenty years later: launched in 2007, it climbed very quickly to close to 50% market share (at the detriment of Nokia and RIM), to start declining in 2012, when Android (Word in 1990) started to dominate the smartphone OS market… Just take a look at this iPhone market share picture by world region in 2019:

But, it was no more possible to call back Steve, very unfortunately (not only for his family, but also for the electronic industry) Resting In Peace. That’s why now, in 2021, Microsoft has decided to acquire Apple (after the Nokia acquisition 8 years ago). By the way, Microsoft is about to rename itself into “GEEC”, to make an image lifting and attract younger people. What’s the acronym signification? “Giant Elegant Elephant Cemetery”…

Eric Esteve from IPNEST

Just a remark… this “breaking news” is obviously a marketing joke, BUT it was inspired by a real news: Apple launching the latest iPhone for €799 and a so called “low cost” version for €499 (I am not sure of the precise pricing, but it’s ridiculously high).

lang: en_US

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Intel Quark: Synthesizable Core?

Intel Quark: Synthesizable Core?
by Paul McLellan on 09-10-2013 at 1:43 pm
Categories: Foundries, Intel Foundry

At IDF Brian Krzanich gave the keynote. I won’t summarize the whole thing here but just talk about one part that was something they had actually managed to keep secret ahead of time: Quark.

Quark is a synthesizable core. It uses 1/10th power of Atom and is 1/5 size. Now I am writing this, I don’t know if this is a fair comparison or one of these “Quark in 14nm is 1/5 size of Atom in 22nm” sort of comparisons. It is designed for new markets such as wearable computing, ingestible and disposable medical devices and the Internet of Things (IoT). I assume it is an Intel Architecture but I have no idea exactly what.

So is Intel entering the processor licensing business? That would be a “no” so the fact that the core is synthesizable isn’t really relevant since only Intel themselves get to synthesize it. During the Q/A someone asked explicitly and Brian confirmed that all the manufacturing would be done by Intel.

“If companies have their own IP then we can support them.” Mostly he seems to mean by writing their own software to run on Quark. Or giving their IP to Intel and having someone there integrate it with the microprocessor. The RTL for the microprocessor is clearly not going to leave the Intel building. Whether it is feasible for a company to do a design around Quark by adding (say) their own network interface seems pretty unclear. We used to do that all the time in the ASIC industry, of course, but there are so many more moving parts in a modern multi-mode multi-corner world with double patterning, FinFETs and lots of other gotchas.

Intel is clearly getting more serious about the foundry business, as in making SoCs for other people. But quite what the business model is here I’m not sure. Intel does the manufacturing. The core may be synthesizable but that flexibility is only going to be used to move it around Intel processes. Or maybe to reconfigure it into different libraries. Intel has its own libraries too, of course (wireless, bluetooth etc). But if the customer has IP of their own, who and how it all gets pulled together remains to be seen.

I also saw a notebook computer running on Intel 14nm silicon, Broadwell I believe. Brian said that it would be shipping by end of 2013. Just what volume remains to be seen. Atom in 14nm will not be available until right at the end of 2014 “as we transition out of the year.”

One other tidbit of information: Brian showed the world’s first 22nm phone with LTE (I have no idea if the LTE is in 22nm or just the application processor, or even if the LTE is in Intel’s process rather than TSMC 28nm). It has 3G voice with LTE data. Next year they will have true voice and data LTE. Currently 35Mb/s with capability to go to 70Mb/s with carrier support. Will be 150Mb/s when by the time it ships in 2014.

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GlobalFoundries Expands in Singapore

GlobalFoundries Expands in Singapore
by Paul McLellan on 09-09-2013 at 8:30 pm
Categories: Foundries, GlobalFoundries

GlobalFoundries has been in Singapore for a long time. Longer than GlobalFoundries has existed in fact. Chartered Semiconductor was started in Singapore in 1987 and GF acquired them in early 2010 less than a year after they were created by spinning out the manufacturing arm of AMD. When GF was started their state of the art fab was in Dresden (Germany) and their new state of the art fab is in New York state. GlobalFoundries is committed to Singapore and is expanding there, investing $500M under the umbrella title Singapore Vision 2015. In the paragraph above I talked about state of the art fabs, but you have to look at the end application too. For power ICs, 180nm is the state of the art process. It is also a big market. The market for analog and power ICs manufactured on mature processes is $45B and is growing at 15% CAGR, faster than the overall semiconductor market. The market is changing too. Most of these specialized chips were manufactured by specialized IDMs, but these designs have moved to process generations beyond what most specialized IDMs have in-house, and so naturally have also migrated to the foundry model just as high complexity SoCs did over the last couple of decades. This is not driven by the latest SoC for your smartphone (those other two fabs are for that) but by all the analog/mixed-signal which is everywhere. In your smartphone for a start… In fact, if you tear down a typical smartphone you’ll find four digital chips (the application processor, the baseband processor (these may be combined) and flash memory. But there are 8 analog chips for everything from power management, display drivers, gyroscopes and so on. But there is also a big analog mixed signal component in storage, automotive, industrial, mil/aero. There are currently 6 GlobalFoundries’ fabs in Singapore (numbered 2, 3, 5, 6, 7 and 3E). The oldest, fab 2, was opened in 1995. The most recent, 3E, in 2008. So what are they doing with that half billion dollar investment?

  • Refreshing the 200mm assets
  • Expanding the 300mm fab 7 giving the benefits of modular process flexibility with 300mm efficiency and scalability
  • Fab 6 will also be converted from 200mm to 300mm
  • That will take Singapore to around 1M 300mm wafers per year (2.6M 8″ equivalents, the “standard” measure) 2/3 of capacity up from 1/3 today
  • Aligning product and manufacturing portfolio in line with target markets with a focus on advanced analog, non-volatile memory, digital, power and RF
  • Reducing manufacturing complexity and increasing manufacturing scalability through a modular technology platform.

Read more about Vision 2015 and Foundry 2.0 here.